In this paper, a model of trellis-coded M-ary PSK (TCM/M-PSK) for digital land mobile communication is realized. Bit error rate(BER) of TCM/M-PSK is calculated theoretically in time selective fading environment due to Doppler spread in the presence of AWGN. cochannel interference. These analyses are employed the receiver with post detection diversity and the direct sequence to improve the BER performance of TCM-MPSK system. It is shown that the CNR required by the diversity reception and the direct sequece(process gain=20dB) TCM-4PSK system is reduced to about 25 dB.

This paper proposes Double queue threshold QLT(Queue Length Threshold) algorithm and Hysteresis effect QLT algorithm. as being DPS(Dynamic Priority Scheduling) techniques. in order to advance the processing of multiple class traffics. Also, the performance of the proposed algorithms is analyzed through computer simulations,and the priority scheduling is analyzed using a retrial queue with two types of calls. Our simulation results show that the performance of the proposed Double queue length threshold QLT algorithm is superior to that of the conventinal QLT algorithm for 2 or more classes delay sensitive traffics. Also we find that Hysteresis effecT QLT algorithm is better mechanism than that of the existing QLT for real time and non-real time traffics.

In this papaer, the input impedance of the rectangular microstrip patch antennas with the multilayered structure is analysed by using the moment method technique in the spectral domain. The analysis is carried out for two different feeding structures : directfeeding structure and electromagnetic-feeding structure. In order to obtain the accurate input impedance, the current distribution on the microstrip feed line is modeled by the quasi-TEM travelling wave and the PWS(piecewise sinusoidal) mode. The input impedances of the designed microstrip antennas are measured and compared with the calculation. which shows a good agreement.

We demonstrate a repeatless transmission of 2.5 Gbps digital signal over 98 km opticla filbers using optical transmitter and optcial receiver which are designed and implemented using commercially available devices. The optical transmitter is realized by using a distributed feedback(DFB) laser. Temperature of the laser is thermoelectrically stabilized and the output optical power is also stabilized by using negative feedback. The output power of the transmitter is 0 dBm. The optical receiver consists of an InGaAs avalanche photodiode, a preamplifier. an automatic gain control amplifier, and a clock/data regenerator. We find an optimum decision threshold that gives the best receiver sensitivity form the measured V curve. The best sensitivity is -35.5dBm( BER-1*10S010T, PRBS=2S023T -1 ) and the overload power is -9 dBm. Finally, we achieve error free optical transmission with 98 km optical fibers. The exinction ration penalty of 2 dB. the chromatic dispersion penalty of 1 dB, and the total power penalty of 3.0 dB are measured. These results satisfy CCITT recommendation.

A theoretical method has been considered for the analysis of a cylindrical edge-slot antenna which belongs to a class of circumferential slot antennas that are suitable for conformal mounting on conducting bodies of revolution. A coupled integral equation is formulated for unknown magnetic currents of both the coaxial aperture and the edge slot, and solved by the moment method. Theoretical values for reflection coefficient obtained based upon the method are compared with our experimental values and other author's results available. There arre good agreement between them.

A curvature variable taper is proposed for a waveguide-microstrip transition. It is applied to a ridge waveguide. The curvature depends on the taper length and difference of waveguide's height and microstrip substrate's height. The taper is manufactured easier than the other tapers. It's reflection coefficient is smaller than the parabolic taper's below one wavelengrh. The results of experiment show that S$_{11}$ is below -20dB and SS$_{21}$ is about -0.5dB in the band of 10~15 GHz. These results are good agreement with the theoritical values.

The characteristics of the shielded suspended substrate strip transmission line(SSSL) are analyzed by the point matching method and the variational method in Quasi-TEM mode. The accuracy of this solution is confirmed by analyzing and comparing this solution with the empirical solution obtained from the same dimension. The characteristic impedance and the effective dielectric constant are also studied by increasing the air-layer height of SSSL.

The scattering problem by E-polarized plane wave with oblique incidence on a tapered resistive strip grating with infinite resistivity at strip-edges is analyzed by the method of moments in the spectral domain. Then the induced surface current density is expanded in a series of Ultraspherical polynomials of the zeroth order. The expansion coefficients are calculated numerically in the spectral domain, the numerical results of the geometricoptical reflection coefficient for the tapered resistivity in this paper are compared with those for the existing uniform resistivity. And the position of sharp variation points in the magnitude of the geometric-optical reflection coefficient can be moved by varying the incident angle and the strip spacing. It is found out that these sharp variation points are due to the transition of higher modes between the propagation mode and the evanescent mode.

Effects of the GaAs semiconductor particles on electrophysical phenomena at the Pt electrode/10S0-3TM KCl aqueous electrolyte interfaces have been studied using voltammetric time based and electrochemical impedance techniques. The anodic decomposition effect f the GaAs semiconductor particles on electrophysical phenomena was significantly observed during the positive potential scan (0 to 1.0 V vs. SCE). On the other hand, the cathodic decomposition effect of the GaAs semiconductor particles was negligible during thenegative potential scan (0 to -1.0 V vs. SCE). The GaAs semiconductor particles act as current activators or mediators during the anodic process and act as charge screens during the cathodic process. The electrolyte resistance and related impedance was increased due to the presence of the GaAs semiconductor particles. The anodic decomposition effect of the GaAs semiconductor particles can directly be applied to activate the hydrogen evolution.

AlAs/GaAs/AlAs RTDs(Resonant Tunneling Diodes) are fabricated and current-voltage properties of them are measured. At room temperature, peak to valley ratio is 2.4 NOT.AND.OR logic gates and Flip-Flop are fabricated using the bistable characteristics of RTDs. Although NOT.AND.OR logic gates need 5~8 transistors. only one RTD is sufficient to fabricate the logic gates. Since the switching time is very short(<10$^12$sec), it is possible to drive the semiconductor circuits fast and integrate them very large. And it is convinced the possibility of integrating RTDs to multilevel logic circuits by observing two peaks of similar current in the serial connection of two RTDs.

We used IR laser inteferometric technique for measuring the temperature of wafer during cryogenic ECR etching. Using this technique, the effect of RF bias power and microwave power on the wafer temperature during etching period is investigated. As the RF bias power and microwave power was increased, the temperature of the wafer considerably increased and we concluded that to prevent the increase of substrate temperature during etching period, an adequate wafer cooling is needed.

We fabricated a large-scale photovoltaic device for detecting-3-5$\mu$m IR, by forming of n$^{+}$-p junction in the $Hg_{1-x}Cd_{x}$Te (MCT) layer which was grown by LPE on CdTe substrate. The composition x of the MCT epitaxial layer was 0.295 and the hole concentration was 1.3${\times}10^{13}/cm^{4}$. The n$^{+}$-p junction was formed by B+ implantation at 100 keV with a does 3${\times}10^{11}/cm^{2}. The n$^{+}$ region has a circular shape with 2.68mm diameter. The vacuum-evaporated ZnS with resistivity of 2${\times}10^{4}{\Omega}$cm is used as an insulating layer over the epitaxial layer. ZnS plays the role of the anti-reflection coating transmitting more than 90% of 3~5$\mu$m IR. For ohmic contacts, gole was used for p-MCT and indium was used for n$^{+}$-MCT. The fabrication took 5 photolithographic masks and all the processing temperatures of the MCT wafer were below 90$^{\circ}C$. The R,A of the fabricated devices was 7500${\Omega}cm^{2}$. The carrier lifetime of the devices was estimated 2.5ns. The junction was linearly-graded and the concentration slope was measured to be 1.7${\times}10^{17}/{\mu}m$. the normalized detectivity in 3~5$\mu$m IR was 1${\times}10^{11}cmHz^{12}$/W, which is sufficient for real application.

In testing for practical scan disigned logic circuits, there may exist logic value constraints on some part of primary inputs due to various requirements on design and test. This paper presents a logic value system called taboo logic values which targets the test pattern generation of logic circuits under logic value constraints. The taboo logic system represents the logic value constraints and identifies additional logic value constraints through the implication of the tqaboo logic values using a taboo logic calculus. Those identified logic value constraints will guide the search during the test pattern generation of avoid the unfruitful searches and to identify redundant faults due to the logic value constraints very quickly. Finally, experimental results on ISCAS85 benchmark circuits will demonstrate the efficiency of the taboo logic values.

This paper presents the design of a placement sysyem integrated in PCB design system. to get an optimal component positioning from part and net list. Unplaced components are placed in initial process using modified cluster development algorithm and are swapped in improvement process using the GFDR(Generalized Force Directed Relaxation) algorithm. The result is optimized in post process by component rotating or pin/gate swapping. Experimental results shwo that the placement system produces manufacturable layouts which are optimal in terms of total routing length.

This paper describes the design of a high-level synthesis system. ISyn: Interface Synthesis System for ISPS-A. which generates hardware satisfying timing constraints. The original version of ISPS is extended to be used for the description/capture of interface operations and timing constraints in the ISPS-A. To generate the schedule satisfying interface constraints the scheduling process is divided into two steps:pre-scheduling and post-scheduling. ISyn allocates hardware modules with I/O ports by the clique partitioning algorithm. Experimental results show that ISyn is capable of synthesizing hardware modules effectively for internal and/or interactive operations.

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.