Since there is currently no commercial protocol simulator for CDMA mobile communication system, we need to develop a General-Purposed Protocol Test Simulator (G-PTS). This paper is concerned with the design and implementation of this G-PTS contains the multi-scenario generating functions, multi-tasking kernel and multiple interface functions. Thus it can be utilized in the test category using multiple base-stations such as soft-handoff, 3-way handoff and mulit-party call features. G-PTS is verified using the model of CDMA soft handoff scenario and the result shows its reliable operations.

Error detection in ARQ(Automatic Repeat Request) protocols is very important in wireless data communication systems. The throughput efficiency of ARQ protocols can be improved by dynamically adapting the protocol packet length so that it approaches the optimum value for throuhput efficiency. In this paper, a simple and novel adaptive packet length allocation method is proposed which transmits the packets with variable length by dyanmically estimating the channel codition. The simulation results show that the average of throughput is improved by 315.4% in the stop-and-wait protocol, 41.4% in the go-back-N protocol and 155.9% in the selective repeat protocol respectively. And the throughput performances of adaptive packet length allocation method approximately approach the theoritically optimal throughput performances.

Diffraction patterns of the copolarized and the crosspolarized total electric fields by a spherical air cavity in a dielectric medium are analyzed in the forward near-field region when the wavelength of the incident plane wave is comparable to one half of the cavity radius. It is shown that double nulls and dips of the copolarized and the crosspolarized total electric fields exist in the measurement plane tansverse to the propagating direction of the incident field, and their dependences on the frequency, the distance of the measurement plane, and the measurement angle are analyzed.

A ray-based approach is developed to calculate the scattering from inhomogeneous dielectric objects. This approach is a natural extension of the "shooting and bouncing ray(SBR)" technique developed earlier for calculating the radar cross section of cavity structures and complex targets. In this formulation, a dense grid of rays representing the incident field is shot toward the scatterer. The curved trajectory, amplitude, phase and polarization of the ray fields inside the inhomogeneous object are computed numerically based on the laws of geometrical optics. The contributions of the exting rays to the exterior scattered field are then calculated by using the equivalence principle in conjunction with " a ray-tube integration" scheme. The ray-based approach is applied for the effect of an arcjet plasma plume on satellite reflector performance and backscattering from inhomogeneous objects.

An X-band highly frequency-stabilized MIC Gunn oscillator using a dielectric resonator is fabricated. Resonant frequency is obrained by a variational method and it is studied how the oscillating characteristics can be affected by several fators. By the optimizing these factors, we can realize the stabilited oscillator output of 250 mW with 5-7 percet efficiency at 10 GHz. It has the favorable characteristics with frequency variation of 70 KHz/$^[\circ}C$ and the ouput variation within 3 dB over the temperature range from 0 to 70$^[\circ}C$.

The operating characteristics, such as, the threshold gain, lasing frequency, and longitudinal intensity profile, etc., of 1.55$\mu$m DFB laser diode with index and/or gain grating structures and with one side AR-coated mirror have been analyzed. From this analysis, the optimum design parameters have been shown that ${\Delta}{\Omega}$ (the phase difference between index grating and gain grating) is 0 or ${\pi}$, (xL)$_{r}$=1~3 and (xL)$_{i}$=0.5~0.9. It has been also shown that the modal selectivity and intensity uniformity of the DFB lasers with .DELTA..OMEGA.=0 are ~1.2 times better thatn those of the DFB lasers with ${\Delta}{\Omega}$= ${\pi}$.

The effects of device geometry and layout on high speed performance such as current gain outoff frequency(f$_{T}$) and maximum oscillation frequency(f$_{max}$) are of very improtant for the scaling-down of geterojunction bipolar transistors(HBT$_{s}$). In this paper AlGaAs/GaAs HBTs are fabricated by MBE epitaxial growth and conventional mesa process, and the experimental data of emitter-base geometru dependency of HBT performance are presented in order to provide the quantitative information for optimum device structure design. It is shown that f$_{T}$ and f$_{max}$ are inversely proportional to the emiter stripe width, while the low emitter perimeter/area ratio is better to f$_{T}$ and worse ot f$_{max}$. It is also demonstrated the f$_{T}$ and f$_{max}$ are highly improved by the emitter-base spacing reduction resulting in less parsitic effects. As the result f$_{T}$ of 42GHz and f$_{max}$ of 23GHz are obtained for fabricated HBT with emitter area of 3${\times}20^{\mu}m^{2}$ and E-B spacing of 0.2$\mu$m.m.m.

Using the Si/SiGe layer grown by solid source molecular beam epitaxy(SSMBE) on the LOCOS-patterned wafers, an emitter-base self-aligned hterojunction biplar transistor(HBT) with the polysilicon-emitter and the silicon germanium(SiGe) base has been fabricated. Trech isolation process, planarization process using a chemical-mechanical poliching, and the selectively implanted collector(SIC) process were performed. A titanium disilicide (TiSi$_{2}$), as a base electrode, was used to reduce an extrinsic base resistance. To prevent the strain relaxation of the SiGe epitaxial layer, low temperature (820${^\circ}C$) annealing process was applied for the emitter-base junction formation and the dopant activation in the arsenic-implanted polysilicon. For the self-aligned Si/SiGe HBT of 0.9${\times}3.8{\mu}m^{2}$ emitter size, a cut-off requency (f$_{T}$) of 17GHz, a maximum oscillation frequency (f$_{max}$) of 10GHz, a current gian (h$_{FE}$) of 140, and an emitter-collector breakdown voltage (BV$_{CEO}$) of 3.2V have been typically achieved.

We fabricated the 1.55.mu.m RWG-DFB-LD and measured its electrical and optical characteristics. Interference fringe of optical beams was used for grating formation and epi layers were grown by lower-temperature LPE. The fabricated RWG-DFB-LD operated in a single longitudinal mode with more than 30dB SMSR at 1543nm emitting wavelength and its threshold current was 40mA. The wavelength shift with operating temperature and characteristic temperature T$_{o}$ were 0.9${\AA}/^{\circ}C$ and 59K, respectively. Linewidth enhancement factor .alpha. and linewidty.optical power product were estimated as 6.15 and 60MHz$\cdot$mW respectively.

The structure of boron ion-implanted pn junctio in the vacancy-doped p-type HgCdTe was investigated with the differential Hall measurement. The as-implanted junction showed the electron concentration as high as 1${\times}10^{18}/cm^{3}$ and the junction depth of 0.6.mu.m. When the HgCdTe junction was heated in oven, the electron concentration near the junction decreased and the junction depth increased as the annealing temperature and time increased. The junction structure after the thermal annealing was n$^{+}$/n$^{-}$/p. For the 200.deg. C 20min annealed sample, the electron mobility was 10$^{4}cm^{2}/V{\cdot}$s near the surface(n$^{+}$), and was larger thatn 10$^{5}cm^{2}/V{\cdot}$s near the junction(n$^{+}$). The junction formation mechanism is conjectured as follows. When HgCdTe is ion-implanted, the ion energy generates crystal defecis and displaced Hg atoms HgCdTe is ion-implanted, the ion energy generates crystal defecis and displaced Hg atoms near the surface. The displaced Hg vacancies diffuse in easily by the thernal treatment and a fill the Hg vacancies in the p-HgCdTe substrate. With the Hg vacancies filled completely, the GfCdTe substrate becomes n-type because of the residual n-type impurity which was added during the wafer growing. Therefore, the n$^{+}$/n$^{-}$/p regions are formed by crystal defects, residual impurities, and Hg vacancies, respectively.

Traveling-wave electrodes for the high-speed Ti:LiNbO$_{3}$ modulators are designed. For a solution to the problems of 1) phase-velocity mismatching between the optical wave and the Modulating M/W, 2) M/W electrode characteristic impedance mismateching, we assume devices with 1$\mu$m thick SiO$_{2}$ buffer layer between the electrode and the Ti:LiNbO$_{3}$ substrate. The electrode analyses are performed by the FEM using the second-order triangular elements. The optimum design parameters to satisfy the phase-velocity matching and the characteristic impedance matching are sought for. By use of the analyses' results, a Mach-Zehnder optical modulator with a CPW electrode is designed as an example. the band-width estimation is also illustrated.

In this paper, we propose an efficient SA(simulated annealing) algorithm for the synthesis of binary phase computer generated hologram. SA algorithm is a method to find the optimal solution through iterative technique. It is important that selecting cost function and parameters within this algorithm. The aplications of converentional SA algorithm to synthesize parameters within this algorithm. The applications of conventional SA algorithm to synthesize binary hologram have many problems because of inappropriate paramters and cost function. So, we propose a new cost function and a calculation technique of proper parameters required to achieve the optimal solution. Computer simulation results show that the proposed method is better than conventional method in terms of diffraction efficiency and reconstruction error. Also, we show the reconstructed images by the proposed method through optical esperiment.

A new nethod, namely multi-gain-levering, is proposed to improve FM response of the single frequency semiconductor lasers and applied to 1.55$\mu\textrm{m}$ InGaAsP/InP MGL(multi-gain-levered)-MQW-DFB-LD. This device consists of three sections with different bandgap energy and can be easily realized by selective MOVPE growth. Our analysis based on Green function showed that a flat, red-shifted, high FM efficiency of aove 15GHz/mA can be extected by novel gain-levering scheme.

A hierarchical placement system based on routing region assignment has been developed to increase the probability of routing completion after placement. While most of the existing placement systems attempt to reduce the cell density at the portions where routing density is high, our method is distinguished in that specific routing regions are allocated to secure complete routing where the routing density is greater than the routing capacity. Hierarchy is vuilt by clustering and recursive paritioning, and the initial placement obtained by partitioning at each level is improved by using the region refinement algorithm. After placement at each hierarchical level, global routing is performed and fouting regions are assigned, if routing density is greater than routing capacity, to be considered at the next level of placement. the proposed algorithm has been implemented and applied to place several industrical gate-array circuits. A couple of circuits which cannot be routed by using conventional placement techniques can be completely routed by using our new placement technique with routing region assignment.

A symbolic layout generator, called Flexible Module Generator (FMG), has been developed for transgorming a given CMOS circuit netlist into an optimized symbolic layout. Contrary to other conventional module generators which place transistors either in horizontal or in vertical direction, FMG places transittors in any hence can multiples of 90$^{\circ}$. This flexible layout style can maximize the diffusion sharing and hence can reduce the wire-length for both of area minimization and performance improvement. In FMG, transistors are initially randomly placed and then selected transistors are iteratively replaced using an optimization technique based on simulated evolution. Whenever a transistor is replaced, the affected nets are rerouted. Constraints on the shape, aspect ratio, and critical path delays are considered during the optimization process. Routing is performed by using a modified maze router on polysilicon, metal 1, and metal 2 interconnection layers. additional routing grids are added, if necessary, for complete routing. Unused rows or columns are removed after routing for area minimization. Experimental reasults show that FMG synthesizes satisfactory layouts.

The leakage current characteristics of the low temperature processed LDD structure poly-Si TFT is analyzed. The excimer laser technology was applied to the recrystallization process of poly-Si film and the maximum processing temperature was retained under 600.deg.C. From the fabricated LDD space 0.3.mu.m to 3$\mu$m, the best on/off current ration could be obtained with the 1.3$\mu$m LDD space. And the threshold voltage did not increase more than 4V over 0.8$\mu$m LDD space. The characteristics of leakage current was compared to non-LDD structure TFT to analyze the mechanism of leakage current. Consequently, it could be concluded that the leakage current is strongly affected by the trap states as well as high electric field between gate and drain.