Protocol specifications and service definitions for distributed open system applications are defined using ASN.1. Therefore, to implement an open system application likes MHS, it is necessary to have well defined encoding/decoding modules which translate ASN.1 protocol specifications into their transfer syntaxes. However, that work is usually tedius, time consuming, and error prone. In this paper, we designed and implemented a new ASN.1 tool set which includes a new ASN.1 run-time library, called HY BER/DER, and an enhanced ASN.1-to-C compiler, called HYASNC$^{+}$. HYASNC$^{+}$ automatically generates C language encoder/decoder stub files and heder files for basic ASN.1 types and subtypes defiend in X.208 recommandation, and all X400 MHS system macro definitions. And, we evaluated the performance of HYASNC$^{+}$ compiler and HY BER/DER run-tiem library, and tested the interoperability of ASN.1 run-time library.

We address an issue of channel sharing among users by using a random assignment-transmitter-based (RA-T) spread-spectrum transmission scheme which permits the contention mode only in the transmission of a header while avoiding collision during the data packet transmission. Once the header being successfully received, the data packet is ready for reception by switching to one of programmable matched-filters. But the receoption may be blocked due to limited number of matched-filters so that this effect is taken into account in our analysis. For realistic analysis, we integrate detection performance at the physical level with channel activity at the link level through a markov chain model. We also consider an acknowledgement scheme to notify whether the header is correctly detcted and the data packet can be processed continuously, which aims at reducing the interference caused unwanted data transmission. It is shown that receiver complexity can be greatly reduced by choosing a proper number of RA codes at the cost of only a little throughput degradation.

This paper proposes a new buffer management scheme to service delay-sensitive traffic and loss-sensitive traffic fairly in ATM networks. The proposed scheme uses tow buffers for delay-sensitive traffic and loss-sensitive traffic. To satisfy the average delay time of delay-sensitive traffic, cells in real-time buffer are served first. When congestion occurs in nonreal-time buffer, low loss priority cell in real-time buffer can be pushed out by high loss priority cell in nonreal-time buffer can be transferred to real-time buffer considering threshold value in real-time buffer. Using computer simulation, the existing methods and proposed scheme are compared and analyzed with respect to cell loss rate and average delay time. Simulation results show that the proposed scheme have superior performance to conventional schemes.

We propose the improved GMSK (gaussian-filtered minimum shift keying) quadrature modulator using the FIR(finite impulse response )filter whose coefficients are obtained form the differnce of phase response, and design its ASIC (applicaton specific integrated circuit) which can be used for GSM (global system for mobile communication) digital cellular system and DCS 1800 (digital cellular system at 1800MHz) personal communication system. Input data become quantized I and Q channel 10 bit signal through cosine and sine ROM mapping after being filtered by the FIR filter whose normalized bandwidth is 0.3 and designed by considering intersymbol interference as well as sampling ratio. These two signals become the GMSK modulated I and Q channel signal through DAC (digital-to-analog converter) and 7th order analog chebyshev LPF(low pass filter) respectively. The difference between the ideal analog signal and its digitized signal is analyzed in terms of sampling noise, quantization noise, truncation noise and coefficient noise. And the effect of the LPF following the DAC is considered. The ASIC design of the GMSK quadrature modulator is also confirmed by an experiment.

Performance analysis of FH/CPFSK system with liiter-discriminator detection and integrate-dump post-detection filtering under the thermal noise and the partial-band noise jamming on the rayleigh fading channel have been analyzed. The thermal noise and partial-band noise jamming, rayleigh fading, intersymbol interference for all eight of the possible adjacent bit data patterns, and FM noise click for evaluating systems have been considered. Also optimum parameters to improve performance of FH/CPFSK system have been obtained and validities for AMPS and CDMA system of land-mobile-communication system through computer simulation have been proved.

In this paper, harmonic-tuning method to achieve the maximum efficiency is proposed. Harmonic tuning method is applied to the optimum load impedance of a class B amplifier, which is extracted by using the modified cripps method. High efficiency power amplifier utilizing GaAs MESFET is designed and fabricated in the 835MHz band. The performance of th eamplifier is presented by having output power of 30.8dBm, drain efficiency of 80.5% and power added efficiency of 66% with an associated power gain of 7.4dB.

In this paper, we design tripel-mode channel filter using iris optimization technique and investigate its response. The cavity diameter is determined to resonate three orthogonal modes coincidently and inter-cavity iris is optimized in which one slot control one TE-TE mode and other TM-TM mode couplings simultaneously. Since the electric/magnectic field is variable due to slot position, the center position of the slot which handle coupling coefficients of two modes should be designe dwith optimizatin technique presented here. The implemented triple-mode filter in this paper saves its mass and volume upto 33% relating to the dual-mode filter, caused by the reduced number of cavities.

This paper presetns the development of a SSPA operating at KU-band(14~14.5 GHz) in order of replace TWTA used in the terrestria transponder of a satellite communication. The driving stage of SSPA uses internally matched 2W, 4W, 8W FET and the power stage is coupled with two internally matched 8W FET by branch-line cominer. The SSPA is fabricated with oth the RF circuit and the bias circuitry operating temperature compensation, regulation and sequence on aluminum housing. The SSPA testing resutls implemented in this way show 24.8$\pm$1dB small-signal gain, 41dBm P1dB power, a typical two tone C/IM3, -33dBc with single carrier backed off 6dB from p1dB, and gain stability over temeprature (-30~50)$\pm$1dB.

Quantum RF impedance of SIS (superconductor insulator superconductor) junction has been analyzed by using through on tucker's quantum mixer theory in the frequency range form 80 GHz to 120 GHz. The embedding impedance of waveguide-type mixer mount and its equivalent circuit have been evaluated. From these evaluated results, the impedance matching efficiency between mixer mount embedding impedance and mixer port impedance of upper-side band and IF which were determined by augmented admittance matrix with given backshort position has been discussed in detail. It is found that the mixer with fixed backshort mount ahs a impedance matching efficiency about 80% at each port of mixer within 85GHz to 115GHz, which implys a conversion los of mixer would be good enough to be operated such a wide band frequency range. Therefore, the theoretical evaluated results show that our method can be used ot design the mixer mount without any mechanical tuning elements such a backshort or an E-plane tunners for wide band operation.

We have evaluated the theoretical conversion loss and noise temperature of mixer using the quantum mixer theory and the method to determine the embedding impedance of waveguide-type mixer mount. At fixed backshort position of the mixer, the calculated SSB mixer conversion loss and mixer noise temperature are 5 dB and 10K within frequency range form 85 GHz to 115 GHz, respectively. The SIS mixer has been developed by using through on the calculated rsutls to observe cosmic radio waves. SIS junction of mixer is Nb/Al-AlOx/Nb and it consists of four series array. Area of each of junction is about 2.5${\mu}m^{2}$. The average receiver noise temperature of manufactured receiver with this mixer is about 30 K(DSB). The receiver noise temperature is much lower than that of receiver with a mixer using mechanical tuning backshort.

When GPS (global positioning system) is used as synchronous signal in CDMA digital cellular base station system and high speed digital synchronous communication network, antenna cable length is increased, comparing with other GPS application such as positioning or car navigation. In this paper, it is proposed that a type of new GPS antenna system including RF stage for reduction of cable loss in case of long cable.The antenna system with TMPA(truncated-corners microstrip patch antenna) is designed and fabricated because GPS signal has RHCP (right-hand circular polarization), consequently antenna size can be made small size. LNA (low noise amplifier) is designed by using HEMT(high electron mobility transistor)which has lower noise figurae and better AGC characteristics at low voltage than GaAs FET, and we equiped mixer, in GPS antenna unit, which converts from 1575.42MHz to 75.42MHz. As result of comparing between typical system and proposed system when cable length is 60m, 63dB, 55dB and 25dB gain are obtained for RG-316/U, RG-58C/U and RG-213/U, and better characteristics are achieved than typical system as far as cable length is longer.

Periodic gratings for 1.55$\mu$m distributed feedback laser diode (DFB LD) have been fabricated by a holographic interference exposure system using an etalon stabilized Ar ion laser. We obtain a good development condition at developer concentration of 65% and obtain etching rate of 1000$\AA$/min at 20.deg. C by the mixed solution HBr:HNO$_{3}$:H$_{2}$O(1:1:10 in volume ratio). We obtain good first order grating with period of 2400${\AA}[\pm}2{\AA}$ at etching time of 45 sec from grating period and diffraction efficiency measurement, and SEM observation of grating fabricated on InP substrate.

The use of holographic interference lithography and removal techniques to corrugate GaAs substrate have been studied. The periodic photoresist structure, which serves as a protective mask during etching, is holographically prepared. Subsequently periodic V-grooved pattern is formed on the GaAs substrate by conventional a H$_{2}$SO$_{4}$-H$_{2}$O$_{2}$-H$_{2}$O wet etching. The linewidth of a GaAs pattern is about 0.4$\mu$m and the depth is 0.5$\mu$m A quantum wires(QWRs) array is well formed on the V-grooved substrate by MOCVD (metalorganic chemical vapor deposition) growth of GaAs/Al$_{0.5}$Ga$_{0.5}$As (50$\AA$/300$\AA$) quantum wells. The formation of QWR array is confirmed by the temperature dependent photoluminescence (PL) measurement. The intensive PL peak with a FWHM of 6meV at 21K shows the high quality of the QWR array.

In the present study, we have studied on the characteristics of BST thin films with various Ba/Sr ratios by using sol-gel method. Barium-acetate, strontium-acetate and titanium isopropoxide are used as starting materials to fabricate BST thin films by sol-gel method. The fabrication conditions are estabilished through the TG-dT analyses and XRD measurements. BST thin films with the Ba/Sr ratios of 90/10, 70/30, 50/50 and 30/70 were deposited on the Pt/Ta/SiO$_{2}$Si substrate with the estabilished sol-gel process, and their characteristics were examined. The relative permittivity and the leakage current density at 5V vary from 287 to 395 and from 2.3 to 220${\mu}$A/cm$^{2}$, respectively, with various Ba/Sr ratio. Among the films investigatd in this research, BST (70/30) thin film shows the best relative permittivity and dielectric loss of BST (70/30) thin film are 395 and 0.045, respectively and the leakage current density at 5V is 2.3${\mu}$A/cm$^{2}$.

To increase the sensitivity and the selectivity of the sensors to TMA gas, the composition ratio and the growth conditions of the ZnO films are studied. Annealing of the ZnO films in the various time ranges and temperatures in the oxygen is carried out to enhance the stbility of the electrical resistance. Pt/Ti heater deposited on backside of the substrates in used to control the operating temperature of th esensor. The ZnO thin film sensors doped to 4.0 wt% $Al_{2}$O$_{3}$ 1.0wt.% TiO$_{2}$ and 0.2wt.% V$_{2}$O$_{5}$ exhibited a high sensitivity and an excellent selectivity for TMA gas. The sensors made with the thin films annealed at 700$^{\circ}$C for 60 minutes in the oxygen atmosphere had a good stability and linearity. The heater deposited in the ratio of 1 to 1 (Pt:Ti) had a good heating properties. The sensors fabricated using above conditions showed a good response to the actual gases of a mackerel at a step of deterioration after death.

A simple analytic model for the planar junctions with multiple foating field limiting rings(FLR) is presented which yields analytic expressions for the breakdown voltage and optimum ring spacings. the normalized potential of each ring is derived as a function of the normalized depletion width and the ring spacing. Based on the assumption that the breakdwon occurs simulataneously at cylindrical junctions of FLR structure where the peak sruface electric fields are equal, the optimum ring spacings are determined. The resutls are in good agreement with the simulations obtained from two dimensional device simulation program MEDICI and with the experimental data reported. The normalized experessions allow a calculation of breakdown voltage and optimum spacing over a broad range of junction depth and background doping levels.

The purpose of this paper is to develop a simulation program to predict resist prifile in electron-beam lithography, where the main issue is proximity effect. The simualtion program composes of monte-carlo simulation, exposure simulation and development simulation. In nonte-carlo simulation, the absorbed energy in the resist is calculated when one electron is incident into resist, using hybrid model on the basis of the rutherford differential scattering cross section and moller theory. In exposure simulation, the absorbed energy in the resist is calculated when electrons are incident in exposure pattern. In the program, the developed profile depending on time is obtained by string model. The 0.2$\mu$m and the 0.3$\mu$m line and space patterns are experimentally delineated and compared to the simulation results to check the relevance of the program.

We propose a mechanism for the formation of pinholes in the Si-buffer layer, through the observations with varying the process- and structure variables in the SEPOX (selective poly-oxidation) process, an isolation method for sub-u DRAMs. Pinholes are formed through the accumulation of Si vacancies generated by the oxidation of Si, in which Si atoms leave the sites (vacancies) at the Si/SiO$_{2}$ interfaces and diffuse into the oxide to be oxidized near interface. In the course of the accumulation of Si-vacancies, the stress induced in the Si-buffer layer affects the migration of vacancies to result in the final size and distribution of pinholes. This paper may be, to our knowledge, the first report about the oxidation-induced pinhole in the Si/SiO$_{2}$ system.

In the conventional GaAs MESFET circuit simulation, the DC and transient simulation results are often failed due to the discontrinuities of the first and second order derivatives arising from the use of separate C-V models in linear, satruration, and transition regions. In this paper, we propose a unified capacitance model for linear, transition, and saturation regions by using a unified channel length modulation effect that is derived by extending the channel length modulation effect in the saturation region to the linear region. Calculated resutls from the proposed capacitance model agree well with 2-D device simulation resutls. Thus, the proposed model is expected to be useful in circuit simulation.

We report the experimental resutls on AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with carbon-doped base structure. To characterize the output power, load-pull mehtod was employed. By characterizing the devices with HP8510C, we extracted the small-signal equivalent circuit. The HBTs were fabricated employing wet mesa etching and lift-off process of ohmic metals. the implementation of polyimide into the fabriction process was accomplished to obtain the lower dielectric constant resultig in significant reduction of interconnect routing capacitance. The fabricated HBTs with an emitter area of 6${\times}14{\mu}m^{2}$ exhibited current gain of 45, BV$_{CEO}$ of 10V, cut-off frequency of 30GHz and power gain of 1 3dBm. To extract the small signal equivalent circuit, the de-embedded method was applied for parasitic parameters and the calculation of circuit equations for intrinsic parameters.

We have characterized XeCl excimer-laser-induced crystallization of thin amorphous silicon films deposited by PECVD (${\alpha}$-Si:H) and LPCVD (${\alpha}$-Si). The electrical properties, surface roughness and crystallinity of crystallized thin films have been measured. The dc conductivities, crystallinity andsurface roughness of the films increased as the laser energy density and shot density were increased. The properties of laser annealed films deposited by LPCVD were better than those of thin films deposite by PECVD. We have also found that the multiple shots with relative low energy density were more benifical to the improsvement of surface roughness than the single shot with high energy density preserving the crystallinity.

In this paper, we propose a new opto-digital object recognition system which has rotation, scale, and shift invariant characteristics. The fourier power spectrum of the object image is modified to get shift invariance. The log-polar transform is used for rotation and scale invariance. And the decision of similarities is performed by nonlinear joint transform correlator (NJTC) that can control the ratio of phase and amplitude signals. Experimental verification of th eproposed optical object recognition system is presented.

We have studied sngle-frequency yield of 1.55${\mu}$m DFB lasers with uniform sinusoidal grating using an effective index transfer matrix method considering both threshold gain difference and spatial hole-burning effect. Optimum grating height and mirror reflectivities that maximize the single-frequency yield are found for a low-reflection (LR)/high-reflection(HR) mirror structure and a LR/as-cleaved miror structure for an assumed basic waveguide structure. LR/HR structure has a high yield of about 80% in a narrow range of grating height while LR/as-cleaved mirror structure has a low yield of about 50% in a relatively wide range of grating height. The effect of the low-reflection facet reflectivity is also studied.

Four types of three-waveguide optical switches are analyzed by measns of the coupled mode theory. Assuming that three proximate waveguides of an optical switch are identical and equally spaced, we examine the switching behavior for both cases where an incident beam is launched into 1) the outer waveguide, 2) the center waveguide. For each beam-launching case, switching voltage is applied so that three waveguides refractive indices be detuned 1) symmetric, 2) anti-symmetric. It is concluded that only three types of optical switches out of four an perform the switching operation. We derive the switching conditions for ach of three possible types and draw the corresponding switching diagrams.

This paper describes a data structure and evaluation algorithm to improve the perofmrances MOS logic-with-timing simulation in computation and accuracy. In order to efficiently simulate the logic and timing of driver-load networks, (1) a tree data structure to represent the mutual interconnection topology of switches and nodes in the driver-lod network, and (2) an algebraic modeling to efficiently deal with the new represetnation, (3) an evaluation algorithm to compute the linear resistive and capacitive behavior with the new modeling of driver-load networks are developed. The higher modeling presented here supports the structural and functional compatibility with the linear switch-level to simulate the logic-with-timing of digital MOS circuits at a mixed-level. This research attempts to integrate the new approach into the existing simulator RSIM, which yield a mixed-klevel logic-with-timing simulator MIXIM. The experimental results show that (1) MIXIM is a far superior to RSIM in computation speed and timing accuracy; and notably (2) th etiming simulation for driver-load netowrks produces the accuracy ranged within 17% with respect ot the analog simulator SPICE.

We presetn sytem-level simulation methodology as well as environment setup established for CDMA digtial cellular mobile station in an effort to verify CDMA modem ASIC design. To make the system-level simulation feasible, behavioral modeling of a microcontroller was first carried out with VHDL. In addition, models written in C language were also developed to provide ASIC with realistic input data. Finally, the netlist of CDMA modem ASIC was loaded on the a hardware accelerator, which was interfaced with VHDL simulator, and ismulation was performed by excuting the actual CDMA call processing software. Simulation resutls thus obtained were confirmed by comparing them with the emulation resutls from the actual system constructed on hardware modeler. these methods were proved to be effective in both discovering in advance malfunctions when embedded in the system or design errors of ASIC and reducing simulation time by a factor of as much as 20 in case of simulation at gate-level.

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

The accuracy of sample-and-hold amplifiers (SHA's) empolying a CMOS process in limited by nonideal factors such as linearity errors of an op amp and feedthrough errors of switches. In this work, after some linearity improvement techniques for an op amp are discussed, three different SHA's for video signal processing are designed, simulated, and compared. The CMOS SHA design techniques with a 12-bit level accuracy are proposed by minimizing cirucit errors based on the simulated results.