• Title, Summary, Keyword: 에러 정정 부호

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Acceleration of ECC Computation for Robust Massive Data Reception under GPU-based Embedded Systems (GPU 기반 임베디드 시스템에서 대용량 데이터의 안정적 수신을 위한 ECC 연산의 가속화)

  • Kwon, Jisu;Park, Daejin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.24 no.7
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    • pp.956-962
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    • 2020
  • Recently, as the size of data used in an embedded system increases, the need for an ECC decoding operation to robustly receive a massive data is emphasized. In this paper, we propose a method to accelerate the execution of computations that derive syndrome vectors when ECC decoding is performed using Hamming code in an embedded system with a built-in GPU. The proposed acceleration method uses the matrix-vector multiplication of the decoding operation using the CSR format, one of the data structures representing sparse matrix, and is performed in parallel in the CUDA kernel of the GPU. We evaluated the proposed method using a target embedded board with a GPU, and the result shows that the execution time is reduced when ECC decoding operation accelerated based on the GPU than used only CPU.

AT-DMB Reception Method with Eigen-space Beamforming Algorithm (고유 공간 빔형성 알고리즘을 이용한 AT-DMB 수신 방법)

  • Lee, Jae-Hong;Choi, Seung-Won
    • Journal of Broadcast Engineering
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    • v.15 no.1
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    • pp.122-132
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    • 2010
  • AT-DMB system has been developed to increase data rate up to double of conventional T-DMB in the same bandwidth while maintaining backward compatibility. The AT-DMB system adopted hierarchical modulation which adds BPSK or QPSK signal as enhancement layer to existing DQPSK signal. The enhancement layer signal should be small enough to maintain backward compatibility and to minimize the coverage loss of conventional T-DMB service coverage. But this causes the enhancement layer signal of AT-DMB susceptible to fading effect in transmission channel. A turbo code which has improved error correction capability than convolutional code, is applied to the enhancement layer signal of the AT-DMB system for compensating channel distortion. However there is a need for other solutions for better reception of AT-DMB signal in receiver side without increasing transmitting power. In this paper, we propose adaptive array antenna system with Eigen-space beamforming algorithm which benefits beamforming gain along with diversity gain. We analyzed the reception performances of AT-DMB system in indoor and mobile environments when this new smart antenna system and algorithm is introduced. The computer simulation results are presented along with analysis comments.

A High Speed Block Turbo Code Decoding Algorithm and Hardware Architecture Design (고속 블록 터보 코드 복호 알고리즘 및 하드웨어 구조 설계)

  • 유경철;신형식;정윤호;김근회;김재석
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.97-103
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    • 2004
  • In this paper, we propose a high speed block turbo code decoding algorithm and an efficient hardware architecture. The multimedia wireless data communication systems need channel codes which have the high-performance error correcting capabilities. Block turbo codes support variable code rates and packet sizes, and show a high performance due to a soft decision iteration decoding of turbo codes. However, block turbo codes have a long decoding time because of the iteration decoding and a complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. After the threshold is decided by a simulation result, the proposed algorithm eliminates the calculation for the bits which have a good channel information and assigns a high reliability value to the bits. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a gaussian one. Also, the proposed algorithm assigns '1', the highest reliable value, to those bits. The hardware design result using verilog HDL reduces a decoding time about 30% in comparison with conventional algorithm, and includes about 20K logic gate and 32Kbit memory sizes.