• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• Journal of Power Electronics
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• v.16 no.2
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• pp.778-785
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• 2016

An excess carrier lifetime extraction method is derived for physics-based insulated gate bipolar transistor (IGBT) models with consideration of the latest development in IGBT modeling. On the basis of the 2D mixed-mode Sentaurus simulation, the clamp turn-off test is simulated to obtain the tail current. The proposed excess carrier lifetime extraction method is then performed using the simulated data. The comparison between the extracted results and actual lifetime directly obtained from the numerical device model precisely demonstrates the accuracy of the proposed method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.413-417
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• 2023

Gallium Oxide (Ga₂O₃) is preferred as a material for next generation power semiconductors. The Ga₂O₃ should solve the disadvantages of low thermal resistance characteristics and difficulty in forming an inversion layer through p-type ion implantation. However, Ga₂O₃ is difficult to inject p-type ions, so it is being studied in a heterojunction structure using p-type oxides, such as NiO, SnO, and Cu₂O. Research the lateral-type FET structure of NiO/Ga₂O₃ heterojunction under the Gate contact using the Sentaurus TCAD simulation. At this time, the VG-ID and VD-ID curves were identified by the thickness of the Epi-region (channel) and the doping concentration of NiO of 1×10¹⁷ to 1×10¹⁹ cm-3. The increase in Epi region thickness has a lower threshold voltage from -4.4 V to -9.3 V at I_D = 1×10^-8 mA/mm, as current does not flow only when the depletion of the PN junction extends to the Epi/Sub interface. As an increase of NiO doping concentration, increases the depletion area in Ga₂O₃ region and a high electric field distribution on PN junction, and thus the breakdown voltage increases from 512 V to 636 V at I_D =1×10^-3 A/mm.