• Communications of the Korean Mathematical Society
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• v.27 no.1
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• pp.69-76
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• 2012

Let R be a ring, and ${\alpha}$ be an endomorphism of R. An additive mapping H : R ${\rightarrow}$ R is called a left ${\alpha}$-multiplier (centralizer) if H(xy) = H(x)${\alpha}$(y) holds for all x,y $\in$ R. In this paper, we shall investigate the commutativity of prime and semiprime rings admitting left ${\alpha}$-multiplier satisfying any one of the properties: (i) H([x,y])-[x,y] = 0, (ii) H([x,y])+[x,y] = 0, (iii) $H(x{\circ}y)-x{\circ}y=0$, (iv) $H(x{\circ}y)+x{\circ}y=0$, (v) H(xy) = xy, (vi) H(xy) = yx, (vii) $H(x^2)=x^2$, (viii) $H(x^2)=-x^2$ for all x, y in some appropriate subset of R.

• Journal of Advanced Navigation Technology
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• v.10 no.4
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• pp.348-355
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• 2006

In this paper, frequency multipliers used S-band transponder of the KOMPSAT 3 are designed and fabricated. In the transponder, 108 times multiplier which generate 1st LO signal(2008.8MHz) is comprised of the X9 frequency multiplier, 1st X2 multiplier, 2nd X2 multiplier and the last stage of the X3 frequency multiplier. As results, output power of 8.17 dBm at 2008.8MHz, the harmonic suppression of -56.67dBc, the bandwidth of 14MHz were measured.

• Journal of the Chungcheong Mathematical Society
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• v.31 no.2
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• pp.247-254
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• 2018

In this paper, we introduce the notion of symmetric bi-multiplier of subtraction algebra and investigate some related properties. Also, we prove that if D is a symmetric bi-multiplier of X, then D is an isotone symmetric bi-multiplier of X.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.29-40
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• 2008

The efficient hardware design of finite field multiplication is an very important research topic for and efficient $f(x)=x^n+x^k+1$ implementation of cryptosystem based on arithmetic in finite field GF($2^n$). We used special generating trinomial to construct a bit-parallel multiplier over finite field with low space complexity. To reduce processing time, The hardware architecture of proposed multiplier is similar with existing Mastrovito multiplier. The complexity of proposed multiplier is depend on the degree of intermediate term $x^k$ and the space complexity of the new multiplier is $2k^2-2k+1$ lower than existing multiplier's. The time complexity of the proposed multiplier is equal to that of existing multiplier or increased to $1T_X(10%{\sim}12.5%$) but space complexity is reduced to maximum 25%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.2
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• pp.3-10
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• 2008

The choice of basis for representation of element in $GF(2^m)$ affects the efficiency of a multiplier. Among them, a multiplier using redundant representation efficiently supports trade-off between the area complexity and the time complexity since it can quickly carry out modular reduction. So time of a previous multiplier using redundant representation is faster than time of multiplier using others basis. But, the weakness of one has a upper space complexity compared to multiplier using others basis. In this paper, we propose a new efficient multiplier with consideration that polynomial exponentiation operations are frequently used in cryptographic hardwares. The proposed multiplier is suitable fer left-to-right exponentiation environment and provides efficiency between time and area complexity. And so, it has both time delay of $T_A+({\lceil}{\log}_2m{\rceil})T_x$ and area complexity of (2m-1)(m+s). As a result, the proposed multiplier reduces $2(ms+s^2)$ compared to the previous multiplier using equally-spaced polynomials in area complexity. In addition, it reduces $T_A+({\lceil}{\log}_2m+s{\rceil})T_x$ to $T_A+({\lceil}{\log}_2m{\rceil})T_x$ in the time complexity.($T_A$:Time delay of one AND gate, $T_x$:Time delay of one XOR gate, m:Degree of equally spaced irreducible polynomial, s:spacing factor)

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.27-35
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• 1997

In this paper, we propose a new scheme for the generation of partial products for VLSI fast parallel multiplier. It adopts a new encoding method which halves the number of partial products using 2x2 submultipliers and rearrangement of primitive partial products. The true 4-input CSA can be achieved with appropriate rearrangement of primitive partial products out of 2x2 submultipliers using the newly proposed theorem on binary number system. A 16bit x 16bit multiplier has been desinged using the proposed method and simulated to prove that the method has comparable speed and area compared to booth's encoding method. Much smaller and faster multiplier could be obtained with far optimization. The proposed scheme can be easily extended to multipliers with inputs of higher resolutions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.747-755
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• 1990

In this paper, we presented a method of constructing a multiplier and an inverse element generator over finite field GF(3**m). We proposed the multiplication method using a descending order arithmetics of mod F(X) to perform the multiplication and mod F(X) arithmetics at the same time. The proposed multiplier is composed of following parts. 1) multiplication part, 2) data assortment generation part and 5) multiplication processing part. Also the inverse element generator is constructed with following parts. 1) multiplier, 2) group of output registers Rs, 3) multiplication and cube selection gate Gl, 4) Ri term sequential selection part. 5) cube processing part and 6) descending order mod F(X) generation part. Especially, the proposed multiplier and inverse element generator give regularity, expansibility and modularity of circuit design.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.2
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• pp.49-61
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• 2009

Finite Field multiplication operation is one of the most important operations in the finite field arithmetic. Recently, Fan and Dai introduced a Shifted Polynomial Basis(SPB) and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. In this paper, we propose a new bit-parallel shifted polynomial basis type I and type II multipliers for $F_{2^n}$ defined by an irreducible trinomial $x^{n}+x^{k}+1$. The proposed type I multiplier has more efficient the space and time complexity than the previous ones. And, proposed type II multiplier have a smaller space complexity than all previously SPB multiplier(include our type I multiplier). However, the time complexity of proposed type II is increased by 1 XOR time-delay in the worst case.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.928-930
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• 2005

With an increasing importance of the information security issues, the efficienct calculation process in terms of finite field level is becoming more important in the Elliptic curve cryptosystems. Serial multiplication architectures are based on the Mastrovito's serial multiplier structure. In this paper, we manipulate the numerical expressions so that we could suggest a 3-times as fast as (3x) the Mastrovito's multiplier using the polynomial basis. The architecture was implemented with HDL, to be evaluated and verified with EDA tools. The implemented 3x GF (Galois Field) multiplier showed 3 times calculation speed as fast as the Mastrovito's, only with the additional partial-sum generation processing unit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.