• Title/Summary/Keyword: 3D integration

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3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • 이강욱
    • 마이크로전자및패키징학회지
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    • 제22권2호
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

ISO 15926 기반 공정 플랜트 3D 설계 정보 통합 플랫폼의 개발 (Development of an ISO 15926-based Integration Platform of 3D Design Data for Process Plants)

  • 김병철;박상진;김봉철;명세현;문두환
    • 한국CDE학회논문집
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    • 제20권4호
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    • pp.385-400
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    • 2015
  • ISO 15926 is an international standard for the integration and sharing of plant lifecycle data. Plant 3D design data typically consist of logical configuration, equipment specifications and ports, and 3D shape data. This paper presents the method for the ISO 15926-based integration of plant 3D design data. For this, reference data (class, attribute, and template) of ISO 15926 were extended to describe plant 3D design data. In addition to the data model extension, a plant design information integration platform which reads plant 3D design data in ISO 15926 and displays 3D design information was developed. Finally, the prototype platform is verified through the experiment of loading and retrieving plant 3D design data in ISO 15926 with the platform.

3D 칩 적층을 위한 하이브리드 본딩의 최근 기술 동향 (Recent Progress of Hybrid Bonding and Packaging Technology for 3D Chip Integration)

  • 정철화;정재필
    • 반도체디스플레이기술학회지
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    • 제22권4호
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    • pp.38-47
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    • 2023
  • Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

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0.75Δ% 굴절율차를 가진 40채널 광파장 다중화 및 역다중화 소자 제작 및 특성 (40channel Arrayed Waveguide Grating with O.75delta% Refractive Index)

  • 문형명;최기선;이길현;김동훈;이지훈;이동환;오진경;곽승찬;권오관;강동수;최준석;정건;이현용
    • 한국광학회지
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    • 제16권3호
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    • pp.196-200
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    • 2005
  • [ $0.75delta\%$ ]의 평판광회로(PLC;Planar Lightwave Circuit)소자의 설계 및 제작기술을 가지고 저손실과 높은 누화율을 가진 파장 다중화 및 역다중화 소자를 개발하였다. C-band AWG(Arrayed Waveguide Grating)에서의 삽입손실은 2.503이하, 누화율은 35dB이상, 균일도는 1dB이하이며 L-band에서는 Vernier 디자인을 적용하여 ITU-T의 파장 정확도가 0.04nm이하가 되도록 제작하였다.

Comparative study of data selection in data integration for 3D building reconstruction

  • Nakagawa, Masafumi;Shibasaki, Ryosuke
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2003년도 Proceedings of ACRS 2003 ISRS
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    • pp.1393-1395
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    • 2003
  • In this research, we presented a data integration, which integrates ultra high resolution images and complementary data for 3D building reconstruction. In our method, as the ultra high resolution image, Three Line Sensor (TLS) images are used in combination with 2D digital maps, DSMs and both of them. Reconstructed 3D buildings, correctness rate and the accuracy of results were presented. As a result, optimized combination scheme of data sets , sensors and methods was proposed.

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Wafer-to-Wafer Integration을 위한 생산수율 챌린지에 대한 연구 (Manufacturing yield challenges for wafer-to-wafer integration)

  • 김사라은경
    • 마이크로전자및패키징학회지
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    • 제20권1호
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    • pp.1-5
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    • 2013
  • 3D integration 기술 특히 W2W integration 기술은 전자산업의 디바이스 scaling 문제를 해결하고 고성능화 소형화 추세에 맞춘 가장 핵심적인 기술 방향이다. 그러나 W2W integration 기술은 현재 가격과 생산수율의 장애를 가지고 있고, 이를 해결하기 위해서 웨이퍼 매칭, 리던던시, 다이 면적 축소, 배선 층 수 축소와 같은 디자인 연구들이 진행되고 있다. W2W integration 기술이 대량생산으로 연결되기 위해서는 우선적으로 웨이퍼 본딩, 실리콘연삭, TSV 배선 공정의 최적화가 이루어져야 하겠지만, 가격을 포함한 생산수율을 높이기 위해서는 반드시 디자인 연구가 선행되어야 하겠다.

슈퍼 칩 구현을 위한 헤테로집적화 기술 (Ultimate Heterogeneous Integration Technology for Super-Chip)

  • 이강욱
    • 마이크로전자및패키징학회지
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    • 제17권4호
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    • pp.1-9
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    • 2010
  • 삼차원 집적화기술의 현황과 과제 및 향후에 요구되어질 새로운 삼차원 집적화기술의 필요성에 대해 논의를 하였다. Super-chip 기술이라 불리우는 자기조직화 웨이퍼집적화 기술 및 삼차원 헤테로집적화 기술에 대해 소개를 하였다. 액체의 표면장력을 이용하여지지 기반위에 다수의 KGD를 일괄 실장하는 새로운 집적화 기술을 적용하여, KGD만으로 구성된 자기조직화 웨이퍼를 다층으로 적층함으로써 크기가 다른 칩들을 적층하는 것에 성공을 하였다. 또한 삼차원 헤테로집적화 기술을 이용하여 CMOS LSI, MEMS 센서들의 전기소자들과 PD, VC-SEL등의 광학소자 및 micro-fluidic 등의 이종소자들을 삼차원으로 집적하여 시스템화하는데 성공하였다. 이러한 기술은 향후 TSV의 실용화 및 궁극의 3-D IC인 super-chip을 구현하는데 필요한 핵심기술이다.

Wafer-Level Three-Dimensional Monolithic Integration for Intelligent Wireless Terminals

  • Gutmann, R.J.;Zeng, A.Y.;Devarajan, S.;Lu, J.Q.;Rose, K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권3호
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    • pp.196-203
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    • 2004
  • A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

GLONASS 측위를 위한 위성좌표 산출 정확도 향상 방안 (Accuracy Analysis of GLONASS Orbit Determination Strategies for GLONASS Positioning)

  • 이호석;박관동;김혜인
    • 한국측량학회지
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    • 제28권6호
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    • pp.573-578
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    • 2010
  • 위성항법시스템에서 정확한 위성궤도결정 기술은 측위 정확도 향상의 필수적인 조건이다. 이 연구에서는 GLONASS의 방송궤도력과 4차 Runge-Kutta 수치적분법을 이용하여 위성좌표를 결정하였으며, 적분간격과 적분시간에 따른 위성궤도의 정확도를 비교하였다. 적분간격에 따른 위성궤도 정확도분석결과, 적분간격이 l초일 때와 300초일 때의 3차원 RMS 오자의 차이가 3cm에 불과한 반면 처리시간은 100배 이상 향상되었다. 적분시간에 따른 위성좌표의 3차원 RMS 오차는 적분시간이 30분, 150분, 300분일 때 각각 8.3m, 187.3m, 661.5m로 나타났으며, 이를 통해 적분시간을 짧게 할수록 정확도가 향상되는 것을 확인하였다. 따라서 이 연구에서는 GLONASS 측위를 위한 위성좌표 결정의 정확도 향상을 위해 적분시간을 최소화할 수 있는 Forward와 Backward 적분을 적용하는 방안을 제안하였으며, 이와 같은 방법을 사용할 경우 5m이하의 위성좌표 산출 정확도를 확보할 수 있다.

A New Smart Stacking Technology for 3D-LSIs

  • Koyanagi Mitsu
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2005년도 ISMP
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    • pp.89-110
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    • 2005
  • A new 3D integration technology using wafer-to-wafer and chip-to-wafer stacking method was described. It was demonstrated that 3D microprocessor, 3D shared memory, 3D image processing chip and 3D artificial retina chip fabricated using 3D integration technology were successfully operated. The possibility of applying 3D image processing chip and 3D artificial retina chip to Robot's eye was investigated. The possibility of implanting 3D artificial retina chip into human eye was investigated.

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