• BMB Reports
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• v.49 no.10
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• pp.542-547
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• 2016

Acid-sensing ion channels (ASICs) are proton-gated cation channels widely expressed in the nervous system. Proton sensing by ASICs has been known to mediate pain, mechanosensation, taste transduction, learning and memory, and fear. In this study, we investigated the differential subcellular localization of ASIC2a and ASIC3 in heterologous expression systems. While ASIC2a targeted the cell surface itself, ASIC3 was mostly accumulated in the ER with partial expression in the plasma membrane. However, when ASIC3 was co-expressed with ASIC2a, its surface expression was markedly increased. By using bimolecular fluorescence complementation (BiFC) assay, we confirmed the heteromeric association between ASIC2a and ASIC3 subunits. In addition, we observed that the ASIC2a-dependent surface trafficking of ASIC3 remarkably enhanced the sustained component of the currents. Our study demonstrates that ASIC2a can increase the membrane conductance sensitivity to protons by facilitating the surface expression of ASIC3 through herteromeric assembly.

• The Magazine of the IEIE
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• v.19 no.6
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• pp.61-68
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• 1992

최근 우리나라의 세계 반도체 시장 점유율이 갈수록 높아지고 있다. DRAM과 같은 경우는 세계 2위 수출국으로 떠올랐다. 이에 따른 선진 외국의 무역 압력이 거세지고 있다. 특히 미국의 경우 미ㆍ일 반도체 협정 체결을 한국에까지 확산하려고 하며, 각종 기술에 대한 특허 제소를 하고 있다. 그러나 국내 반도체 산업은 DRAM부분에 집중되어 있어서 기술 집약적인 ASIC 부분은 취약하다. 또한 세계의 반도체 시장중에서 ASIC이 차지하고 있는 비중이 갈수록 커지는 현상에 미루어 보아 빠른 시일내에 ASIC 부분을 강화해야 할 필요성이 있다. 본고에서는 국내에 도입된 ASIC 설계 환경을 살펴본 후, 현재 추진되고 있는 새로운 ASIC 설계 환경을 고찰한다. 또한 ASIC 설계 환경에서 중요한 역할을 하는 ASIC CAD환경에 대하여 살펴보기로 한다.

• Electronics and Telecommunications Trends
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• v.3 no.2
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• pp.116-133
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• 1988

ASIC (Application Specific Integrated Circuit)은 직역하면 응용특정 IC, 혹은 특정용도 IC로서 LSI시장의 조사회사인 Dataquest사가 '84년경부터 사용하기 시작한 말이다. ASIC이 최근 크게 주목을 끌고있는 것은, 반도체 사용자가 자신의 제품에 개성을 불어넣기 위해서는 범용IC를 사용해온 것으로는 기술적 우위성이 확보되지 않는다고 판단했기 때문에 주문형 LSI를 강하게 추진해 왔다는 것과 반도체 메이커도 메모리IC를 중심으로 한 범용IC시장의 부진, 더우기 날로 더해가는 반도체 시장의 시장쟁탈 및 무역마찰로 인해 ASIC 시장에로의 참여가 강화되어 왔다는 점 등을 들수있다. 집적화 기술은 매년 진보하여 지금은 100만개 이상의 트랜지스터를 집적할 수 있게 되었다. 따라서 지금까지 SSI/MSI를 사용해서 회로설계한 기능단위의 칩을 프린터 기판위에 조합시켜 시스팀을 구축해 왔으나, 앞으로는 하나의 칩위에 시스팀을 구성하는 시대로 변하고 있다. ASIC은 그 요청에 따라서 one-chip화의 개념에 따라서 만들어진 것으로서, 시장환경에 대단히 유익한 디바이스로 생각할 수 있다. 시스팀의 one-chip화의 실현결과 압도적으로 소형화, 경량화, 성자원화가 달성됨과 동시에 신뢰성 및 동작성능도 우수하게 되었다. ASIC기술은 현재 주류로 되어있는 게이트 어레이를 볼때, 개발비용은 크게 감소하여 개발기간도 논리회로가 완성된다면 3~4주 정도로 단축시킬수 있다. ASIC 설계에는 각 공정에 있어서 고도의 컴퓨터 지원설계가 채용되고 제조공정에서는 첨단의 프로세서 기술 등이 이용되므로 ASIC기술은 종합적인 첨단기술의 집약이라고 불러도 좋을것이다. 이러한 기술추세에 맞추어 전자통신 동향분석지 제3권 제1호(1988.3.)에 발표된 최신 ASIC기술동향의 후속편으로 ASIC에 관련된 중요용어 50개를 선정, 알파벳 순으로 나열하여 설명하였다.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.695-701
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• 1988

본 연구에서는 구조적 표현의 화상 처리 알고리즘인 BF(Breadth First) 선형 4진 트리 알고리즘(BFQT 알고리즘)의 압축, 재생부를 하드웨어화 하여 ASIC(Application Specific Integrated Circuit)을 설계한다. ASIC과 IBM PC와의 인터페이스를 명시하며, 새로운 하드웨어 알고리즘을 도입하여 ASIC의 세부구조를 설계한다. 소프트웨어로 수행할 때 보다 제안된 ASIC으로 수행할 때가 압축은 약 21배, 재생은 약 4배 빨라지는 것으로 추정된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1597-1602
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• 1999

An analog / digital mixed mode frequency multiplication and distribution ASIC for switch link or network synchronization of ATM switching system for B-ISDN has designed. This ASIC generates 234-7 MHz system clock and 77.76 MHz, 19.44 MHz user clocks using 46.94 MHz external clock. It also includes digital circuits for checking and selecting between the two external clocks. For effective ASIC design, full custom technique is used in analog PLL circuit and standard cell based technique is used in digital circuit. Resistors and capacitors are specially designed so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.220-229
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• 1996

We presetn sytem-level simulation methodology as well as environment setup established for CDMA digtial cellular mobile station in an effort to verify CDMA modem ASIC design. To make the system-level simulation feasible, behavioral modeling of a microcontroller was first carried out with VHDL. In addition, models written in C language were also developed to provide ASIC with realistic input data. Finally, the netlist of CDMA modem ASIC was loaded on the a hardware accelerator, which was interfaced with VHDL simulator, and ismulation was performed by excuting the actual CDMA call processing software. Simulation resutls thus obtained were confirmed by comparing them with the emulation resutls from the actual system constructed on hardware modeler. these methods were proved to be effective in both discovering in advance malfunctions when embedded in the system or design errors of ASIC and reducing simulation time by a factor of as much as 20 in case of simulation at gate-level.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.1885-1896
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• 1996

This paper describes the implementation of the AVT(Automatic video Tracker) using ASIC. The basic tracking algorithm is based on the spatio-temporal gradient method, and adaptive window sizing, track state decision algorithm were also realized. Newly developed ASIC performs recursive image filtering, extraction of spatio-temporal gradient/gradient functions of image in field rate. Using the FPGA/ASIC, the tracker was simply realized in one board type which can be easily applied to various image system. We conformed ASIC operation by computer simulation and tested the system in real tracking situations. From the result, the system can track the moving target which has a velocity of 2-3 pixel/field and a size of varying from 2 to 128 pixes. Also fast refresh rateof motion estimation(60Hz) improves the characteristics of servoing system which forms feedback loop with the tracker.

• The KIPS Transactions:PartD
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• v.9D no.1
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• pp.161-166
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• 2002

The existing method in PN code acquisition process have a problem in PN code acquisition time because PN code searching is accomplished in one epoch. In this paper, we propose algorithm that can reduce PN code acquisition time because PN code searching is accomplished in each other two epoches. The designed ASIC chip using proposed algorithm confirmed that the area (the number of gates) increase more than existing method in PN code acquisition, but the performance of PN code acquisition is better than existing method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.929-935
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• 2003

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.522-530
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• 2009

In this paper, we propose an efficient methodology to fix timing violation in ECO step for ASIC process. Timing violation can occur from various reasons and the major cause is inconsistent correlation between EDA tools. The most frequent violation is setup time and hold time violation. First, we analyzed the reason of violation creation, and then proposed the adjusting method for overcome them. Each violation can be fixed by increasing data required time or decreasing data arrival time. We proposed the detailed technique on a case basis. It is difficult to execute these methods by routine of algorithm or principle. Therefore ASIC engineer needs to apply these technique to violation as conditions of the implemented design.