• Journal of Animal Science and Technology
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• v.53 no.2
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• pp.107-111
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• 2011

This study was undertaken to reveal the relationship between genetic variations and the basic coat color classification system in Jeju horses. Genetic variations of the melanocortinreceptor 1 (MC1R) and agouti signaling protein (ASIP) genes were investigated using pyrosequencing technique. A nucleotide substitution mutation for MC1R g.901C>T and an ASIP 11-bp deletion mutation were screened. Black horses had MC1R $E^+$/- ($E^+/E^+$ or $E^+/E^e$) and ASIP $A^a/A^a$ genotypes. In contrast, chestnut horse genotypes were MC1R $E^e/E^e$ and ASIP -/-. Thus, black and bay horses have at least one dominant MC1R allele, $E^+$, whereas chestnut horses have homozygous recessive alleles $E^e/E^e$. This suggests that the MC1R genotypes determine chestnut or black/bay coat color, regardless of the genotype distribution of ASIP. In addition, the horses with MC1R $E^+$/- and a dominant ASIP $A^A$/- allele showed bay coat color, but not black, suggesting that the ASIP $A^A$ allele represses black coat color development in the hairs of the body, but not in the mane and all four legs. Pedigree analysis showed a consistent relationship between the genotype distribution of the MC1R and ASIP genes and basic coat color patterns, even in the $F_1$ progeny. The results of this study revealed the relationship between the coat color phenotype and genetic background and suggested that useful information may be provided for molecular breeding of Jeju horses.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.06a
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• pp.79-84
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• 2003

이 논문은 빠른 ASIP(application specific instruction processor) 평가를 위한 재적응성을 가진 컴파일러/시뮬레이터 환경에 대해 이야기한다. ASIP의 성능은 하드웨어 구조뿐만 아니라, 수행되는 응용 소프트웨어에 영향을 받기 때문에, 높은 성능의 ASIP 개발을 위해서는 컴파일러 및 시뮬레이터의 개발이 선행되어야 한다. 그러나 다양한 ASIP 구조에 따라 적합한 고성능의 컴파일러/시뮬레이터를 만드는 일은 매우 시간 소모적인 일이 될 뿐만 아니라, 오류가 발생하기도 쉽다. 본 논문에서는 HiXR2라는 ADL(architecture description language)을 이용하여 명령어 구조를 기술하고 이를 바탕으로 컴파일러와 시뮬레이터를 자동 생성하였다. HiXR2의 재적응성 및 생성된 컴파일러/시뮬레이터의 정확성을 검증하기 위하여 ARM9 프로세서와 CalmRISC32 프로세서 구조를 각각 기술하고, 각각에 대하여 응용프로그램 코드를 컴파일 및 시뮬레이션 하는 예제를 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9B
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• pp.939-946
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• 2009

In this paper, we propose a new network ASIP(Application Specific Instruction-set Processor) which was designed for simulation models by a machine descriptions language LISA(Language for Instruction Set Architecture). This network ASIP is aimed for an exclusive engine undertaking packet processing in a router. To achieve the purpose, we added a new necessary instruction set for processing a general ASIP based on MIPS(Microprocessor without Interlock Pipeline Stages) architecture in high speed. The new instructions can be divided into two groups: a classification instruction group and a modification instruction group, and each group is to be processed by its own functional unit in an execution stage. The functional unit was optimized for area and speed through Verilog HDL, and the result after synthesis was compared with the area and operation delay time. Moreownr, it was allocated to the Macro function ana low-level standardized programming language C using CKF(Compiler Known Function). Consequently, we verified performance improvement achieved by analysis and comparison of execution cycles of application programs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.45-53
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• 2003

This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.

• Journal of Life Science
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• v.21 no.4
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• pp.494-501
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• 2011

To understand the relationship between coat color inheritance patterns and genotypes of Extension (E) and Agouti (A) loci in cattle, the genotypes for melanocortin-1 receptor (MC1R) and agouti signaling protein (ASIP) were analyzed in Hanwoo, Jeju black cattle (JBC), and their crossbred progeny. Three MC1R alleles ($E^D$, $E^+$, and e) were found in the black-colored JBC population. JBC had no recessive homozygotes (e/e), but this genotype was predominant in the Hanwoo breed. However, MC1R $E^+$/e Hanwoo did not produce a black coat color as they appeared either as brown or solid red. For ASIP, three genotypes (A/A, A/$A^{Br}$, and $A^{Br}/A^{Br}$) were determined by insertion/deletion of an L1-BT element in Hanwoo. The ASIP $A^{Br}$ allele was rarely observed, and no ASIP $A^{Br}/A^{Br}$ homozygotes were detected in the JBC population. Cattle carrying ASIP $A^{Br}$ did not show any agouti-like brindle pigmentation patterns in either breed or their progeny. The coat colors of the crossbred progeny were discriminated by two colors, yellowish-brown versus dark-brown or black, and their coat colors were directly related to the genotypes of the Extension locus, yellowish-brown (e/e) and dark-brown or black ($E^+$/e), but not to the Agouti locus. ASIP genotypes probably did not affect coat color development in the Hanwoo or crossbred progeny. Our results suggest that the ASIP genotypes do not play key roles in coat color variation, but the MC1R genotypes do direct the phenotypes of Hanwoo, JBC, and their progeny.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.106-111
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.913-921
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• 2007

Retargetable compiler which generates executable code for a target processor and performance profiler are required to design a processor optimized for a specific application. This paper presents an architecture exploration methodology based on ADL (Architecture Description Language). We synthesized instruction set and optimized processor structure using information extracted from application program. The information of operation sequences executed frequently and register usage are used for processor optimization. Architecture exploration has been performed for JPEG encoder to show the effectiveness of the system. The ASIP designed using the proposed method shows 1.97 times better performance.

• Electronics and Telecommunications Trends
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• v.24 no.6
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• pp.94-98
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• 2009

최근 모바일 멀티미디어 기기들의 사용이 증가하면서 고성능 멀티미디어 프로세서에 대한 필요성이 높아지고 있는 추세이다. DSP 기반의 시스템은 범용성에 기인하여 다양한 응용 분야에서 사용될 수 있으나 주문형반도체 보다 높은 가격과 전력소모 그리고 낮은 성능을 가진다. ASIP는 주문형반도체의 저비용, 저전력, 고성능과 범용 프로세서의 유연성이 결합된 새로운 형태의 프로세서로서, 단일 칩 상에 H.264, VC-1, AVS, MPEG 등과 같은 다양한 멀티미디어 비디오 표준 및 OFDM과 같은 통신 시스템을 지원하고 또한 고성능의 처리율과 계산량을 요구하는 차세대 비디오 표준의 구현을 위한 효과적인 해결책으로 주목되고 있다. 본 기술 문서에서는 ASIP의 특징과 애플리케이션의 가속 방법, ASIP을 위한 컴파일러 설계 및 응용에 관하여 기술한다.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.4
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• pp.292-298
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• 2017

The complexity of image compression algorithms has increased in order to improve image compression efficiency. One way to resolve high computational complexity is parallel processing. However, entropy coding, which is lossless compression, does not fit into the parallel processing form because of the correlation between consecutive symbols. This paper proposes a new application-specific instruction set processor (ASIP) platform by adding new context-adaptive binary arithmetic coding (CABAC) instructions to the existing platform to quickly process a variety of entropy coding. The newly added instructions work without conflicts with all other existing instructions of the platform, providing the flexibility to handle many coding standards with fast processing speeds. CABAC software is implemented for High Efficiency Video Coding (HEVC) and the performance of the proposed ASIP platform was verified with a field programmable gate array simulation.