• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.121-130
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• 2012

In this paper, the structure of the Aladdin system was modeled by Petri nets for performance evaluation of 40G bps class Aladdin system which was developed in ETRI as the high-speed DDoS defensive tool. The efficiency analysis of the system architecture according to the input traffic of the Aladdin system was performed based on the modeling.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.992-995
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• 2011

ALADDIN(Advanced Layer-free DDoS Defense INfrastructure) 시스템은 양방향 10Gbps 트래픽을 처리할 수 있는 안티 DDoS 전용 시스템이다. 로드 밸런서 엔진, 안티 DDoS 분석 엔진, PCI-Express 엔진으로 구성된 세 개의 FPGA 기반 하드웨어 엔진과 소프트웨어 엔진으로 이루어진 시스템은 인라인 모드로 동작하면서 Wire-speed 로 패킷을 처리한다. 시스템은 네트워크 레벨의 DDoS 공격뿐만 아니라 어플리케이션 레벨의 DDoS 공격도 실시간으로 탐지하고 대응한다. 본 논문에서는 ALADDIN 시스템의 설계 및 구현, 테스트 결과에 대해 기술한다.

• The KIPS Transactions:PartC
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• v.18C no.3
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• pp.127-134
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• 2011

Malicious botnet has been used for more malicious activities, such as DDoS attacks, sending spam messages, steal personal information, etc. To prevent this, many studies have been preceded. But malicious botnets have evolved and evaded detection systems. In particular, HTTP GET Request attack that exploits the vulnerability of the application layer is used. ALAB of ALADDIN proposed by ETRI is DDoS attack detection system that HTTP GET, Incomplete GET request flooding attack detection algorithm is applied. In this paper, we extend Incomplete GET detection algorithm of ALAB and derive the optimal configuration parameters to verify the validity of the algorithm ALAB by the study of the normal and attack packets.

• Publications of The Korean Astronomical Society
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• v.21 no.2
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• pp.67-74
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• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).