• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4B
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• pp.637-646
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• 2010

For 40 Gb/s data transmission through electrical backplane trace up to 40 inch length on four layer fire-resistant (FR-4), we have designed the 40 Gb/s backplane channel model consisting of four channel 10 Gb/s. Simulation results show an enhancement of backplane channel characteristics excellent more than requirements specified in IEEE P802.3ba at 10 Gb/s. This paper provides a review of the structures and algorithms used in receive and adaptive equalization for 40 Gb/s backplane Ethernet. The use of this backplane channel model could achieves better receive equalizer at great data rate than 10 Gb/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7A
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• pp.741-747
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• 2004

This paper will discuss the Design and Implementation of common Backplane for TDM/Data System. Transmission performance of over 10Gbps in proposed commom or converged backplane architecture was discussed and demonstrated using readily available components.

• Journal of Information Display
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• v.12 no.4
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• pp.213-217
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• 2011

Printing technologies were applied to fabricate a flexible organic thin-film transistor (OTFT) backplane for electrophoretic displays (EPDs). Various printing processes were adopted to maximize the figures of each layer of OTFT: screen printing combined with reverse offset printing for the gate electrodes and scan bus lines with Ag ink, inkjet for the source/drain electrodes with glycerol-doped Poly (3,4-ethylenedioxythiophene): Poly (styrenesulfonate) (PEDOT:PSS), inkjet for the semiconductor layer with Triisopropylsilylethynyl (TIPS)-pentacene, and screen printing for the pixel electrodes with Ag paste. A mobility of $0.44cm^2/V$ s was obtained, with an average standard deviation of 20%, from the 36 OTFTs taken from different backplane locations, which indicates high uniformity. An EPD laminated on an OTFT backplane with $190{\times}152$ pixels on an 8-in panel was successfully operated by displaying some patterns.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1263-1270
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• 2000

The operation frequency of High-speed Communication System becomes very fast with the advanced technology of VLSI chips and system implementation. There may exist various types of noise sources degrading the signal integrity in this system. The present main system is made of backplane, so faults can be brought whenever a board is removed, replaced or added. This backplane boards testing is a very important process to verify the operation of system. firstly, we model the effects of the internal noises in the High-speed Communication System to the signal line and propose a new design method to minimize these effects. For the design methodology, we derive the characterization value for each mode land them construct the optimal simulation model. We compare the result of own proposing method with that fo the existing methods, through simulation and show that the quality of High-speed Communication System is significantly enhanced. Secondary our proposing BIST for the Backplane Boards Testing is designed to guarantee that there is no fault in the high-speed communication system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2B
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• pp.197-209
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• 2010

In this paper, We have designed and analyzed a characteristics of backplane channel having 40 inch strip line length of four lanes and Flame Retardant four (PR-4) material, and have designed 40 Gb/s Receive and adaptive equalizer and its high-speed equalization algorithm using the backplane channel characteristics. For 40 Gb/s high-speed data communications pass through the backplane, a 10Gb/s 4 channel receive & equalizer with DFE except for FFE was proposed. This receive and equalizer meets the requirements of the IEEE Std P802.3ba standard-based receive equalizer to implement equalizers on the receive end of a 46 inch length's backplane channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2518-2524
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• 2009

This paper presents the backplane effects due to a rectangular aperture size for two-wire transmission line with equal line length crossing the changeable rectangular aperture in an infinite ground backplane. It is used to determine the characteristics of the backplane insertion loss of the transmission line from the load section in accordance with the backplane aperture size. The results show that the insertion gain and insertion loss are obtained for the specific frequency range when the transmission line is closed to the backplane aperture size. The insertion loss is decreased that the aperture horizontal length and vertical length is more than a=50 mm and b=20 mm. The measurements of insertion loss are performed to verify the theoretical analysis.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.2
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• pp.237-243
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• 2008

This paper presents the backplane effects for two-wire transmission line with different line length crossing the rectangular aperture in an infinite ground backplane. The FDTD method is used to determine the characteristics of the backplane insertion loss and return loss of the transmission line in accordance with the transmission line spacing and additional wire lengths. The results show that the insertion gain is obtained for the narrow spacing of the transmission line and the insertion loss is appeared for the transmission line with the additional wire The measurements of return loss are performed to verify the theoretical analysis.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.683-684
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• 2016

The up-to-date high-performance DSP or FPGA employs SRIO(Serial Rapid IO) as a high-speed serial communications. SRIO is an industry standard regulated upto Ver 3.1. In this study we developed a backplane having a transmission rate to 15Gbps based on a TI DSP. The back plane icould be used to High-speed video transmission, and will be adopted to connecting multiple DSPs for scalable architecture. This paper will discuss the design constraints for a high-speed communication and multiple-core operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.355-358
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• 2003

본 문서는 백프레인(backplane)에서 프로세서 HSTL(High-speed Transceiver Logic)의 데이터 전송 및 수신 특성을 알아보기 위해 HSPICE를 사용하여 시뮬레이션을 하였으며 Xilinx Virtex II XC2V FF896 FPGA를 이용하여 직접 제작 신호 전달특성을 분석하였다. PCB(Printed Circuit Board)는 FR-4를 사용하였으며 point to point 배선 길이에 대해 데이터 전송속도 특성을 시험하였고 구현 가능한 데이터 전송 및 수신 한계 속도에 대해 검토하였다. 시험결과 point to point 접속 신호 전송 및 수신 한계속도에 영향을 주는 것이 배선 길이와 주변 전기적 잡음이 중요한 역할을 함을 알 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.363-365
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• 2003

본 문서는 백프레인(backplane)에서 프로세서 버스(bus)의 데이터 전송 및 수신 특성을 알아보기 위해 HSPICE를 사용하여 시뮬레이션 하였다. 백프레인은 FR-4를 사용하였으며 버스 배선 길이와 스터브(stub) 길이에 대해 데이터 전송속도 특성을 시뮬레이션 하였다. 그리고, 구현 가능한 데이터 전송 및 수신 한계 속도에 대해 검토하였다. 시험결과는 백프레인에서 버스 한계속도에 영향을 주는 것이 버스에 연결된 스터브 길이와 수가 중요한 역할을 함을 알 수 있었다.