• International Journal of Internet, Broadcasting and Communication
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• v.6 no.2
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• pp.10-12
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• 2014

This work is based on the motion estimation to handle the ill-posed nature. The algorithm used in this study that performs the motion estimation for overlapped block is used to calculate with using pixel of neighborhood block with higher correlation and present block by considering the correlation level of neighborhood block. The proposed method shows in a significant improvement in the quality of the mothion field when comparing the conventional methods.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.3
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• pp.144-149
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• 1998

This paper presents a fast motion estimation algorithm, 5DS, useful for video coding. We first try block matching to 4 directions(N, E, W, S) to estimate motions in this algorith, since most of motions in video are oriented to those direction, and then try one additional diagonal matching between the matching ponts having small MADs. It makesthis algorithm possible for searching through a diagonal direction which is not adequate to logarithmic (LOG) search algorithm. This proposed algorithm has almost same PSNR but, 1.9, 1.2 times faster than classical block matching methods such as three steps search(TSS) and LOG search algorithms.

• Journal of Broadcast Engineering
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• v.3 no.1
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• pp.85-92
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• 1998

The block matching algorithm is the most popular motion estimation method in image sequence coding. In this paper, we propose a VLSI architecture. for implementing a recently proposed fast bolck matching algorith, which uses spatial correlation of motion vectors and hierarchical searching scheme. The proposed architecture consists of a basic searching unit based on a systolic array and two shift register arrays. And it covers a search range of -32~ +31. By using the basic searching unit repeatedly, it reduces the number of gatyes for implementation. For basic searching unit implementation, a proper systolic array can be selected among various conventional ones by trading-off between speed and hardware cost. In this paper, a structure is selected as the basic searching unit so that the hardware cost can be minimized. The proposed overall architecture is fast enough for low bit-rate applications (frame size of $352{\times}288$, 3Oframes/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic searching unit, the architecture can be used for the higher bit-rate application of the frame size of $720{\times}480$ and 30 frames/sec.