• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.385-390
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• 2013

This paper proposes an efficient hardware architecture of CABAC for HEVC decoder. The proposed method is structured to handle two bins in one cycle, while preserving data dependencies of the CABAC. In addition, the processing time of the proposed architecture is reduced because the operation using Offset and Range is processed while the architecture reads rLPS from rLPSROM. As a result of analyzing operating frequency of the proposed CABAC architecture, the proposed architecture has improved by 40% than the previous one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.771-777
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• 2012

This paper proposes a binary arithmetic encoder of CABAC using a Common Operation Unit including the three modes. The binary arithmetic encoder performing arithmetic encoding and renormalizer can be simply implemented into a hardware architecture since the COU is used regardless of the modes. The proposed binary arithmetic encoder of CABAC includes Context RAM, Context Updater, Common Operation Unit and Bit-Gen. The architecture consists of 4-stage pipeline operating one symbol for each clock cycle. The area of proposed binary arithmetic encoder of CABAC is reduced up to 47%, the performance of proposed binary arithmetic encoder of CABAC is 19% higher than the previous architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.6C
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• pp.355-360
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• 2011

In this paper, we propose a new context-based adaptive binary arithmetic coding (CABAC) method for lossless image compression. Since the conventional CABAC in H.264/AVC was originally designed for lossy coding, it does not yield adequate performance during lossless coding. Therefore, we proposed an improved CABAC method for lossless intra coding by considering the statistical characteristics of residual data in lossless intra coding. Experimental results showed that the proposed method reduced the bit rate by 18.2%, compared to the conventional CABAC for lossless intra coding.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.934-937
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• 2015

본 논문은 비디오 디코더의 병목현장을 해결하고 대량의 데이터를 처리할 수 있는 다중병렬처리방식의 HEVC CABAC 디코더를 소개한다. CABAC 디코더를 병렬화한 하드웨어 VLSI구조를 설계하여 크기 대비 높은 처리량이 나오는지를 설계 및 분석결과를 통해 연구결과를 도출하는 게 본 논문의 목적이다. CABAC 디코더 내부 module(산술 디코더, 문맥 모델러, 역이진화기) 1개에서 4개까지의 병렬화를 분석한 결과 4개의 병렬화를 했을 때가 크기 대비 처리량이 가장 높다는 것을 알 수 있었다. 또한 내부 module 4개를 병렬화한 CABAC 디코더 4개를 병렬화하여 slice 단위로 나눠진 프레임 1개를 한 번에 처리하는 방식을 채택하였다. 본 논문에서는 각 CABAC 디코더의 내부 module 4개를 병렬화하고, 병렬화한 CABAC 디코더 4개를 다시 병렬화하는 하드웨어 구조를 사용한다.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• Journal of IKEEE
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• v.19 no.4
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• pp.583-589
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• 2015

In the HEVC CABAC, the probability model is updated after a bin is encoded and next bin is encoded based on the updated probability model. Conventional CABAC encoders can encode only one bin per cycle, which cannot increase the encoding throughput. The probability model does not need to be updated in the bypass bins. In this paper, a HEVC CABAC encoder is proposed to increase encoding throughput by parallel processing of bypass bins. The designed CABAC encoder can process either a regular bin or maximum 4 bypass bins in a cycle. On the average, it can process 1.15~1.92 bins in a cycle. Synthesized in 0.18 um technology, its gate count, maximum operating speed, and the maximum throughput are 78,698 gates, 136 MHz, and 261 Mbin/s, respectively.

• Journal of Broadcast Engineering
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• v.12 no.4
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• pp.377-380
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• 2007

In this paper, an improved CABAC is proposed for the lossless compression in H.264/AVC. CABAC in the lossless coding is not as efficient as that in the lossy compression since it was developed for lossy coding. CABAC for the lossless coding in H.26과/AVC Advanced 4:4:4 Profile is applied without the change of the conventional binarization method. Thus, a binarization method considering the statistical characteristic of residual signals is proposed for the lossless coding in 0.264/AVC Advanced 4:4:4 Profile. The experimental results show that the proposed method obtains approximately 3.4% bitrate reduction in comparison to that of the conventional lossless coding.

• Journal of IKEEE
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• v.19 no.2
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• pp.254-259
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• 2015

CABAC is a context-based adaptive binary arithmetic coding method. It increases the encoding efficiency by updating the probability based on the information of the previously coded symbols. Context modeler is a core block of CABAC, which designs a probability model according to the symbol considering statistical correlations. In this paper, an efficient hardware architecture of CABAC context modeler is proposed. The proposed context modeler was designed in Verilog HDL and it was implemented in 0.18 um technology. Its gate count is 29,832 gates including memory. Its operating speed and throughput are 200 MHz and 200 Mbin/s, respectively.

• Journal of IKEEE
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• v.20 no.3
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• pp.326-329
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• 2016

HEVC CABAC encoder performs binary arithmetic encoding after syntax elements are converted into binary values. Therefore, in HEVC CABAC decoder, binarized syntax elements from binary arithmetic decoder should be de-binarized into original syntax elements in the de-binarizer. In this paper, a HEVC CABAC de-binarizer architecture was proposed and implemented. It consists of a controller that analyzes and merges binarized syntax elements and an engine that converts merged binarized syntax elements into original syntax elements. The designed de-binarizer was described in Verilog HDL and it was synthesized and verified in 0.18um process technology. Its gate count and maximum operating frequency are 3,114 gates and 220 MHz, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.