• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.125-129
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• 2008

A low-voltage active CMOS inductor approach, which can improve the quality-factor(Q), is proposed in this paper. A low-voltage active inductor circuit topology with a feedback resistance is proposed, which can substantially improve its equivalent inductance and quality-factor(Q). This proposed low-voltage active inductor with a feedback resistance was simulated by ADS(Agilent) using 0.18um standard CMOS technology. Simulation showed that the designed active inductor had a maximum quality-factor(Q) of 3000 with a 1.5nH inductance at 4GHz

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.873-876
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• 2005

This paper presents a new current transient test technique for wideband CMOS Op Amps. This technique monitors the transient power supply current and output responses of the CMOS Op Amp to automatically differentiate faulty and fault-free op amps. The wideband op amp is designed using 0.25${\mu}$m CMOS technology. We present detailed simulation results for a wideband op amp. We show that catastrophic faults in op amps can be detected and analyzed by monitoring power supply currents and output responses. This technique is inexpensive and simple.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.4
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• pp.602-610
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• 1993

The DDA of new active element and the DDA differential integrator are designed. The DDA can be improved matching problems of external elements in op-amp application circuits. The design of DDA is used the transconductance element, differential pair and $2{\mu}m$ design rule. In order to evaluate the performance of the CMOS DDA, we simulated the DDA voltage inverter and the DDA level shifter using the designed CMOS DDA. Furthermore, the grounded resistor and the differential integrator is designed using the CMOS DDA and we found that its characteristics are agreed to OP-AMP differential integrator's. We performed the layout of the CMOS DDA and DDA differential integrator with MOSIS $2{\mu}m$ CMOS technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.180-183
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• 2000

Beginning with a brief introduction on near 100 nm or below CMOS devices, this paper addresses novel devices for future sub-100 nm CMOS. First, key issues such as gate materials, gate dielectric, source/drain, and channel in Si bulk CMOS devices are considered. CMOS devices with different channel doping and structure are introduced by explaining a figure of merit. Finally, novel device structures such as SOI, SiGe, and double-gate devices will be discussed for possible candidates for sub-100 nm CMOS.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.467-468
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• 2008

In this paper, a logic family, the transmission gate CMOS(TG CMOS) is proposed, which combines the transmission gate and pass transistor resulting in a different configuration from traditional full CMOS. In the simulation, basic cells comprising this logic are designed and their dynamic responses are analyzed. The simulation shows their performance is exceeding that of conventional full CMOS.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.10
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• pp.1888-1892
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• 2008

In this paper, a new parallel CMOS self-bias differential amplifier is designed to use in high-speed analog signal processing circuits. The designed parallel CMOS self-bias differential amplifier is developed by using internal biasing circuits and the complement gain stages which are parallel connected. And also, the parallel architecture of the designed parallel CMOS self-bias differential amplifier can improve the gain and gain-bandwidth product of the typical CMOS self-bias differential amplifier. With 1.8V $0.8{\mu}m$ CMOS process parameter, the results of HSPICE show that the designed parallel CMOS self-bias differential amplifier has a dc gain and a gain-bandwidth product of 64 dB and 49 MHz respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.184-195
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• 1996

Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• Electrical & Electronic Materials
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• v.8 no.2
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• pp.204-210
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• 1995

The characteristics of the internal circuits and the load capacitance should be included to optimize the size of BiCMOS buffer. In order to get the optimum size and delay time of the BiCMOS buffer, new size plane is suggested. By using the size plane, the optimum characteristics of CMOS buffer according to the number of stages can be obtained. From this method, delaytime, .tau.$_{D}$, is obtained 2.39 nsec with $V_{\var}$=5V, $C_{L}$=5pF, W=30.mu.m and $A_{e}$=135.mu. $m^{2}$.>..>...>.