• 전자공학회논문지B
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• 제28B권11호
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• pp.859-865
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• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• 전자공학회논문지A
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• 제33A권4호
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• 대한전자공학회논문지
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• 제21권5호
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• pp.55-60
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• 1984

CMOS기술의 발전에 따라 디지탈 회로를 실현하는데 complex gate 구조를 많이 사용하게 되었다. CMOS complex gate에 대해 내부 게이트 응답과 unknown state등을 고려하여 모든 stuck-open(이하 s-op)과 stuck-on(이하 s-on) 고장을 검출할 수 있는 새로운 테스트 생성 알고리즘이 제소되었다 이 알고리즘은 minimal하고 complete한 테스트 집합을 구할 수 있게 해준다. 또한, 임의의 CMOS complex gate 회로에 대해 본 알고리즘을 적용시켜, 컴퓨터를 통해 그와 같은 테스트 집합이 구해짐을 입증하였다.

• 전자공학회논문지C
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• 제34C권1호
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• pp.1-11
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• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.118-119
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• 2007

High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

• 한국위성정보통신학회논문지
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• 제10권2호
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• pp.30-33
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• 2015

본 논문에서는 Hybrid RF기반 CMOS 카메라를 이용한 피부질환 모니터링 시스템 개발에 대한 연구를 수행하였다. Hybrid RF통신기반 CMOS 카메라를 이용한 영상 전송 기법에 대하여 제시하였으며, 이와 더불어 CMOS 카메라를 이용한 피부질환 모니터링을 위한 원격 모니터링이 가능한 스마트폰 App을 개발하였다. Hybrid RF통신방식을 이용한 영상전송방식은 WiFi통신방식을 적용하여 CMOS 카메라로부터 취득된 영상 정보를 스마트폰 App을 통하여 모니터링할 수 있도록 구성하였다. 피부질환 모니터링 스마트폰 APP은 WiFi통신방식을 이용하여 언제 어디서나 원격 모니터링이 가능하다. 본 논문에서 제안한 Hybrid RF통신기반 CMOS 카메라를 이용한 피부질환 모니터링 시스템은 내시경 응용 활용 사례로서 널리 활용될 수 있을 것으로 예상된다.

• 한국정밀공학회지
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• 제20권5호
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• 한국전기전자재료학회논문지
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• 제11권6호
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• 전자공학회논문지SC
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• 제37권2호
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• pp.60-68
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• 2000

본 논문에서는 표준 메모리 공정에 구현이 가능한 CMOS 전류원의 설계 기법에 대해 논한다. 제안하는 설계기법은 자기바이어스 기법을 활용하여 공급전압의 변화에 대해 매우 좋은 특성을 갖고, 새로운 온도보상 기법을 통해 온도변화에 대한 출력전류 변이의 일차성분을 제거할 수 있으며, 칩 내의 전압잡음에 강한 새로운 전류감지 스타트업 회로를 포함한다. 이러한 CMOS 전류원의 회로설계 기법과 함께 제안된 CMOS 전류원을 초고속 DRAM의 클록 발생회로에 적용할 수 있는 방법에 대해서도 논의한다. 본 논문에서 제안된 CMOS 전류원의 설계기법은 해석적인 방법과 함께 회로 시뮬레이션을 통해 그 유용성을 입증한다.

• 대한전자공학회논문지
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• 제26권2호
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• pp.118-123
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• 1989

본 논문에서는 저소비 전력이고 회로설계가 용이한 CMOS 회로를 이용하여 음성신호 처리용 SCF를 집적화 할때 OP AMP를 디지탈 부분과 공존할 수 있도록 ${\pm}$5V로 전원을 설정하여 CMOS OP AMP의 설계예를 들고 설계방법에 의해 구한 MOS 트랜지스터의 채널폭과 길이를 설계회로에 적용하여 LAYOUT 하였으며 시뮬레이션을 통하여 동작특성을 조사하였다. 또한 이 설계법은 주어지는 설계조건에 따라 설계 되어지므로 다른 용도의 CMOS OP AMP 설계에도 이용되어질 수 있을 것이다.