• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2181-2186
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• 2006

In this paper, a RTL binding technique for CPLD constraint is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in used CLB.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.799-802
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• 1998

본 논무은 HLS에서 CPLD 조건식을 고려한 RTL바인딩 기술로서 HDL로 기술된 회로의 스케쥴링을 한후 모듈 연산 간격을 고려하여 합당한 모듈을 선택하고 스케쥴링과 할당을 수행한 후 주어진 조건식에 맞도록 CPLD를 선정한다. 또한 할당된 결과의 모듈을 CPLD 내부의 CLB의 크기를 고려하여 부울식을 분할하고 최적의 CLB를 사용하여 회로를 구현할 수 있도록 binding 알고리즘을 제안하였다.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.1-6
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• 2006

In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm.

• Proceedings of the Korean Society of Computer Information Conference
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• 2017.01a
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• pp.145-146
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• 2017

본 논문에서는 CPLD 구조를 고려한 게이트 레벨 글리치 제거 방법에 대해 제안하였다. CPLD는 AND-OR 게이트의 2단 구조를 가진 LE를 기본 구조로 구성되어 있는 소자이다. CPLD로 구현할 회로에 대한 DAG를 CPLD 구조에 맞도록 그래프를 분할하여 매핑가능클러스터를 생성한다. 생성된 매핑가능클러스터는 내부의 글리치와 전체 회로에 대한 글리치 발생 가능성을 검사하여 글리치를 제거한다. AND게이트와 OR게이트를 사용하는 2단 구조는 게이트가 달라 글리치가 발생될 수 있는 가능성을 검사하기 어렵다는 단점이 있어 AND-OR 게이트의 2단 구조와 동일한 구조를 가지고 있으며 게이트가 동일한 NAND 게이트를 이용하여 전체 회로를 변환한 후 글리치 발생여부를 검사함으로서 정확한 글리치 발생 가능성을 제거한다. 실험 결과는 제안 된 알고리즘 [10]과 비교하였다. 소비 전력이 2 % 감소되어 본논문에서 제안한 방법의 효율성이 입증되었다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1165-1168
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

• Journal of the Korea Society of Computer and Information
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• v.10 no.2 s.34
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• pp.49-57
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• 2005

In this paper. a CLB-based CPLD low power technology mapping algorithm for trade-off is proposed. To perform low power technology mapping for CPLD, a given Boolean network has to be represented to DAG. The proposed algorithm consists of three step. In the first step, TD(Transition Density) calculation have to be Performed. Total power consumption is obtained by calculating switching activity of each nodes in a DAG. In the second step, the feasible clusters are generated by considering the following conditions : the number of output. the number of input and the number of OR-terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. The proposed algorithm is examined by using benchmarks in SIS. In the case that the number of OR-terms is 5, the experiments results show reduction in the power consumption by 30.73$\%$ comparing with that of TEMPLA, and 17.11$\%$ comparing with that of PLAmap respectively

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.3
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• pp.43-48
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• 2000

In this paper, CPLD(Complex Programmable Logic Device) controller designed with VHDL is developed. With the controller, the harmonics from 3 phase diode rectifier are suppressed and power factor is also improved. The input current of diode rectifier is drawn from the ac mains only during the period in the ac cycle when the instantaneous voltage is greater than the voltage across the dc-link capacitor. The three bidirectional switches rated at very small power are installed in a conventional three phase diode rectifier. Using CPLD controller, an idle current charges to capacitors continuously. Results of simulation and experimental demonstrate a reduction of harmonics, a improvement of power factor and THD.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.1-5
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• 2013

In this paper a study of efficient CPLD low power algorithm is proposed. Proposed algorithm applicate graph partition method using DAG. Circuit representation DAG. Each nodes set up cost. The feasible cluster create according to components of CPLD. Created feasible cluster generate power consumption consider the number of OR-term, the number of input and the number of output. Implement a circuit as select FC having the minimum power consumption. Compared with experiment [9], and power consumption was decreased. The proposed algorithm is efficient. this paper, we proposed FPGA algorithm for consider the power consumption.

• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.161-166
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• 2006

In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.