• Title/Summary/Keyword: Capacitance design

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The Design and Performance Verification of Collocated Capacitance Sensor for Magnetic Bearing (자기베어링과 공위한 축전센서의 설계 및 성능 평가)

  • 유선중;신동원;김종원
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1994.10a
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    • pp.317-322
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    • 1994
  • The design and performance verification of collocated capacitance sensor system for magnetic bearing is presented. Noncollocation between actuators and sensors may cause unstable rotor behavior. The capacitance sensor is not affected by magnetic field. PCB type capacitance sensor is installed between magnetic bearing polse. so, collocation of sensors and actuators can be achieved. Experiment of sensor's static and dynamic charactistics is conducted. Modeling of the rotor system supported by magnetic bearing is made. And performance comparison between simulation and experiment is showed.

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A Study on Optimal Design of Capacitance for Active Power Decoupling Circuits (능동 전력 디커플링 회로의 커패시턴스 최적 설계에 관한 연구)

  • Baek, Ki-Ho;Park, Sung-Min;Chung, Gyo-Bum
    • The Transactions of the Korean Institute of Power Electronics
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    • v.24 no.3
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    • pp.181-190
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    • 2019
  • Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

Development of Capacitance Measuring Equipment for Electrostatic Precipitator

  • Kim, Seung-Min;Lee, Sung-Jin;Nam, Jung-Han;Cho, Chang-Ho
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.128.2-128
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    • 2001
  • Since pulse energization can improve the performance of Electrostatic Precipitator(ESP) for high resistivity dusts, high voltage micro-pulse generators, 70kV 140usec duration pulses for instance, are commonly developed by LC resonance for most pulse powered ESPs. Consisting of discharge electrodes and collecting electrodes, ESP has its own capacitance like a capacitor. ESP's capacitance affects the LC resonance phenomenon with resonance inductor and capacitor of micro-pulse power supply, engineers should acquire the value of their ESP to design for proper power supply design. In this study, we describe the ESP's capacitance measuring device which has the same topology with our new developed micro-pulse power supply. In this microcontroller based capacitance measuring equipment, ESP's capacitance can be calculated easily through ...

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Design Guidelines for a Capacitive Wireless Power Transfer System with Input/Output Matching Transformers

  • Choi, Sung-Jin
    • Journal of Electrical Engineering and Technology
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    • v.11 no.6
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    • pp.1656-1663
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    • 2016
  • A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

A Design Guide of 3-stage CMOS Operational Amplifier with Nested Gm-C Frequency Compensation

  • Lee, Jae-Seung;Bae, Jun-Hyun;Kim, Ho-Young;Um, Ji-Yong;Sim, Jae-Yoon;Park, Hong-June
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.1
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    • pp.20-27
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    • 2007
  • An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.

Parasitic Capacitance Analysis with TSV Design Factors (TSV 디자인 요인에 따른 기생 커패시턴스 분석)

  • Seo, Seong-Won;Park, Jung-Rae;Kim, Gu-Sung
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.4
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    • pp.45-49
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    • 2022
  • Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

A Study on a Capacitance Displacement Sensor for the Ultraprecision Measurement (초정밀 측정용 정전용량 변위센서에 관한 연구)

  • An, Hyung-Jun;Jung, Yoon;Jung, Sung-Chun;Jang, In-Bae;Han, Dong-Chul
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1996.11a
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    • pp.291-295
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    • 1996
  • This paper discusses several design factors of a capacitance displacement sensor with a numerical method and several experiments and describes guide lines of the design of this type sensor. We introduce the charge density method for the analysis of this type sensor, which has feasible accuracy and efficiency. The analysis of this type sensor with the charge density method agrees with displacement sensitivity experiments of a circular plate capacitance sensor with the sensor amp based In the charge transfer principle.

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The Design of Capacitance Variation Detector for the Obstacle Detection System (방해물 감지 장치용 캐패시턴스 변화 감지기의 설계)

  • Kim, Jae-Min;Song, Yun-Seob;Yi, Sang-Yeoul;Kim, Soo-Won
    • Journal of Sensor Science and Technology
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    • v.13 no.2
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    • pp.133-138
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    • 2004
  • Today, the obstacle detection system has massive size and restrictive detection range. To solve these problems, this paper proposes the capacitance variation detector using the variated capacitance value as a result of the obstacle approaching. If obstacle approaches, the capacitance value of capacitance sensor is increased and the operating frequency of oscillator is decreased. Then this changed frequency appears to the output of the mixer that operate down conversion. The capacitance variation detector is produced by Hynix$0.35{\mu}$ CMOS process. In experiment result, the frequency of final output is 6.81 MHz at no obstacle and 31.45 MHz at approaching obstacle. In conclusion, proposed capacitance variation detector has small size, low power consumption and easiness to set up anywhere. So it is expected to substitute the obstacle detector.

The Effects of Smoking on Bioelectrical Capacitance Measured at Twelve Source Points: A Cross-Over Study (흡연이 십이원혈(十二原穴)의 체표 capacitance에 미치는 영향)

  • Kim, Yang-Seob;Park, Young-Chun;Yim, Yun-Kyoung
    • The Journal of Korean Medicine
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    • v.36 no.3
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    • pp.35-52
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    • 2015
  • Objectives: The objective of this study was to investigate the effects of smoking on the skin bio-electrical capacitance at twelve source points. Methods: Twenty healthy male subjects were assigned to smoking and sham-smoking by a random cross-over design. Skin bio-electrical capacitance was measured at twelve source points for 10 minutes before and after smoking. The change of skin bio-electrical capacitance was analysed. Results: 1. The skin bio-electrical capacitance at LU9, PC7 and LR3 was significantly increased after smoking. 2. In the smoking group, the skin bio-electrical capacitance at the source points of Hand Yin meridians significantly increased compared to that of Foot Yin and Hand Yang meridians. Conclusions: Smoking significantly increased the skin bio-electrical capacitance at the source points of Lung, Pericardium and Liver meridians. Hand Yin meridians appear to be more vulnerable to smoking than other meridians.

A Study on Reactor Capacitance Estimation Algorithm and 5kW Plasma Power Supply Design for Linear Output Control of Wide Range (넓은 범위의 선형 출력 제어를 위한 5kW 플라즈마 전원장치 설계 및 반응기 커패시턴스 추정 알고리즘의 관한 연구)

  • Noh, Hyun-Kyu;Lee, Jun-Young;Kim, Min-Jea
    • The Transactions of the Korean Institute of Power Electronics
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    • v.21 no.6
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    • pp.514-524
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    • 2016
  • This work suggests a study on 5 kW plasma power supply design and reactor capacitance estimation algorithm for a wide range of linear output control to operate a plasma reactor. The suggested study is designed to use a two-stage circuit and control the full-bridge circuit of the two-stage circuit using the buck converter output voltage of the single-stage circuit. The switching frequency of the full-bridge circuit is designed to operate through high-frequency switching and obtain maximum output using LC parallel resonance. Soft switching technique(ZVS) is used to reduce the loss caused by high-frequency switching, and duty control of the buck converter is applied to control a wide range of linear output. The internal capacitance of the reactor cannot easily be extracted, and thus, the reactor cannot be operated in an optimized resonant state. To address this issue, this work designs the internal capacitance of the reactor such that estimations can be performed with the developed reactor capacitance estimation algorithm applied to the internal capacitance of the reactor. A 5 kW plasma power supply is designed for a wide range of linear output control, and the validity of the study on the reactor capacitance estimation algorithm is verified.