• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.04b
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• pp.477-480
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• 1995

Dccisions of optimal filling conditions for the chip encapsulation have been done primarily by an ad hoc use of expertise accumulated over the years because the chip encapsulation process is quite complicated. The current CAE systems do not provide mold designers with necessary knowledge of the chip encapsulation for the successful design of optimal filling except flow simulation capability. There have been no attempts to solve the optimal filling problem in the process of the chip encapsulation. In this paper, we have constructed an design system for optimal filling to avoid short shot in the chip encapsulation process which combines an optimization methodology with CAE software.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.43-48
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• 2002

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.154-159
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• 2003

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.2
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• pp.99-106
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• 1998

In this paper, we have constructed an expert system for semiconductor chip encapsulation which combines a knowledge-based system with CAE software. The knowledge-base module includes heuristic and pre analysis knowledge for evaluation and redesign. Evaluation of the initial design and generation of redesign recommendations can be developed from the rules as applied to a given chip package. The CAE programs can be used for simulating the filling and packing stage of encapsulation process. The expert system is a new tool which enables package design or process conditions with high yields and high productivity.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.12
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• pp.13-21
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• 1996

In this paper, methods to reduce wire sweep during the chip-encapsulation process have been studide. Two methods have been tried for this purpose, namely runner balancing and ram velocity control. Runner balancing has been achieved automatically by using a computer program. Ram-velocity control has been achieved using empirical rules and results from a flow simulation of the encapsulation process. A mold which has 12 cavities for chip has been used as a case study. The simulation results show that the wire sweep obtained from the optimal process condition is about 1/5 of that from initial, unoptimized condition.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.17-22
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• 2000

In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.

• Journal of the Korean Society for Precision Engineering
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• v.12 no.12
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• pp.91-99
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• 1995

An effort has been made to more accurately analyze the flow in the chip cavity, particularly to model the flow through the openings in the leadframe and correctly treat the thermal boundary condition at the leadframe. The theoretical analysis of the flow has been done by using the Hele- Shaw approximation in each cavity separated by a leadframe. The cross-flow through the openings in the leadframe has been incorporated into the Hele-Shaw formulation as a mass source term. The temperature of the leadframe has been calculated based on energy balance in the leadframe. The flow behavior in the leadframe has been verified experimentally. In the experiment, a transparent mold and clear fluid have been used for flow visualization. Comparisons were made between the calculation and experimental results which showed a good agreement.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.588-592
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• 1996

In this paper, we have constructed an expert system for semiconductor chip encapsulation which combines a knowledge-based system with CAE software. The knowledge-base module includes heuristic and pre-analysis knowledge for evaluation and redesign. Evaluation of the initial design and generation of redesign recommendations can be developed from the rules as applied to a given chip Package. The CAE programs can be used for simulating the filling and packing stage of encapsulation process. The expert system is a new tool which enables package design or process conditions with high yields and high productivity.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.67-72
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• 2001

An Effort has been made to more accurately analyze the flow in the chip cavity, particularly to model the flow through the openings in the leadframe and correctly treat the thermal boundary condition at the leadframe. The theoretical analysis of the flow has been done by using the Hele-Shaw approximation in each cavity separated by a leadframe. The cross-flow through the openings in the leadframe has been incorporated into the Hele-Shaw formulation as a mass source term. The optimization program based on the complex method integrated with flow analysis program has been successfully used to obtain the optimal filling conditions to avoid short shot.