• Journal of IKEEE
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• v.25 no.4
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• pp.689-696
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• 2021

In this paper, in order to apply Prognostics and Health Management(PHM) to an electronic system or circuit, a circuit capable of detecting and predicting defect characteristics inside the system or circuit is implemented, and the results are described. In the previous study, we demonstrated that the frequency of the amplitude of S-parameter changed as the circuit defect progressed. These characteristics were measured by network analyser. but in this study, even if the same defect detection method is used, a circuit is proposed to check the progress of the defect, the remaining time, and the occurrence of the defect without large measurement devices. The circuit is designed to detect the change in impedance that generates changes of S-parameter, and it is verified through simulation using the measurement results of Bond-wires.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.64-70
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• 1997

This paper presents a parameter optimization method using evolutionary programming in voltage reference circuit because the designer must select appropriate parameter values of the circuit taking into consideration both powr voltage and temperature variation. In this paper, evolutionary programming is suggested as an approach for finding good parameters with which the reference voltage variation is small with respect to temperature variation. Simulation results. Simulation results show that this method is effective in circuit design.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.623-627
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• 1995

This paper describes analysis and optimization of Weil-Dobke synthetic testing circuit parameters, which is efficient and economical test method in high capacity AC circuit breaker. In this paper, analysis of synthetic short-circuit test circuit parameter proposed nondimensional factor that is reciprocal comparison value of circuit parameter and is not related to rated of circuit breaker, in particular, this study induce minimization of required energy of critical TRV generation specified in IEC 56 standards and present optimal design of synthetic short circuit testing facilities.

• Journal of Electrical Engineering and Technology
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• v.8 no.4
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• pp.799-807
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• 2013

The proper equivalent circuit is newly presented for electro-magnetic resonance based wireless power transfer. Based on the proposed equivalent circuit of open-ended helical antennas, the parameter identification of helical antennas can be well derived for highly efficient wireless power transfer. The well-established equivalent circuit in high frequency ranges is developed for analyzing a resonance enhanced-electromagnetic coupling helical antennas and the unknown parameters for helical antennas are identified by experiments. The effectiveness based on the proposed equivalent circuit is verified through experiments.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.3
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• pp.177-182
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• 2003

In the case of the flash memory, various kinds of transistors and the wide range of operation voltage are necessary to achieve the read/write operations. Therefore, the characteristics of transistors are measured in the silicon for the circuit design, and the test vehicle run must be processed. In this study, an efficient design flow is suggested using TCAD tools. The test vehicle is replaced with well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for flash memory device. The calibration errors are less than 5% of a full chip operation, which is accepted by the designers. The results of the calibration were used to predict I-V curves and model parameter of the various transistors for the design of flash device.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.3
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• pp.123-127
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• 2001

The prediction method of the parameter C/sub gs/ of CMOS transistor is proposed by calculating the mobil charge in inversion layer of COMS transistor. This parameter C/sub gs/ decided on the cutoff frequency in MOS transistor in RF range and coupled input and output. This parameter C/sub gs/ in RF range is very important parameter in small signal circuit model. This proposed method is contributed to developing software of extracting parameter value in equivalent circuit model. The method provide the important information to construct a RF nonlinear model for multifinger gate MOSFET. This method will be very valuable to develop a large signal MOSFET model for nonlinear RF IC design.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1242-1244
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• 1999

AVR parameter tuning for voltage control of power system generators has generally been done with the open-circuit model of the synchronous generator. When the generator is connected on-line and operating at rated load conditions, the AVR operates in an entirely different environment from the open-circuit conditions. This paper describes a new method for AVR parameter tuning using optimization technique with on-line linearized system model. As this method considers not only the on-line models but also the off-line open-circuit models, AVR parameters tuned by this method can give the sufficiently stable performance at the open-circuit commissioning phase and give the desired performance at the operating conditions. Also this method estimates the optimum parameters for desired performance indices that are chosen for satisfying requirements in some practical applications, the performance of the AVR can satisfy the various requirements.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.80-82
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• 1988

This paper proposed a new equivalent circuit and parameter estimation for I.M, which is different from T type and L type equivalent circuits. By using this circuit, we can analyze the torque of I.M, such as seperately exited D.C Motor, further more, we think that this equivalent circuit is effective to the vector control system for I.M.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.1
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.