• Title/Summary/Keyword: Circuit testing improvement

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Applying Parallel Processing Technique in Parallel Circuit Testing Application for improve Circuit Test Ability in Circuit manufacturing

  • Prabhavat, Sittiporn;Nilagupta, Pradondet
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.792-793
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    • 2005
  • Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

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A study on New Non-Contact MR Current Sensor for the Improvement of Reliability in CMOS VLSI (CMOS회로의 신뢰도 향상을 위한 새로운 자기저항소자 전류감지기 특성 분석에 관한 연구)

  • 서정훈
    • Journal of the Korea Society of Computer and Information
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    • v.6 no.1
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    • pp.7-13
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    • 2001
  • As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.

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Stator Shape Optimization for Electrical Motor Torque Density Improvement

  • Kim, Hae-Joong;Kim, Youn Hwan;Moon, Jae-Won
    • Journal of Magnetics
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    • v.21 no.4
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    • pp.570-576
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    • 2016
  • The shape optimization of the stator and the rotor is important for electrical motor design. Among many motor design parameters, the stator tooth and yoke width are a few of the determinants of noload back-EMF and load torque. In this study, we proposed an equivalent magnetic circuit of motor stator for efficient stator tooth and yoke width shape optimization. Using the proposed equivalent magnetic circuit, we found the optimal tooth and yoke width for minimal magnetic resistance. To verify if load torque is truly maximized for the optimal tooth and yoke width indicated by the proposed method, we performed finite element analysis (FEA) to calculate load torque for different tooth and yoke widths. From the study, we confirmed reliability and usability of the proposed equivalent magnetic circuit.

Quality and Productivity Improvement by Clustering Product Database Information in Semiconductor Testing Floor

  • Lim, Ik-Sung;Koo, Il-Sup;Kim, Tae-Sung
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.23 no.60
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    • pp.73-81
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    • 2000
  • The testing processes for VLSI finished devices are considerably complex because they require different types of ATE to be linked together. Due to the interaction effect between two or more linked ATEs, it is difficult to trace down the cause of the unexpected longer ATE setup time and random yields, which frequently occur in the VLSI circuit-testing laboratory. The goal of this paper is to develop and demonstrate the methodology designed to eliminate the possible interaction factors that might affect the random yields and/or unexpected longer setup time as well as increase the productivity. The statistical method such as design of experiment or multivariate analysis cannot be applied to the final testing floor here directly due to the environmental constraints. Expanded product data information (PDI) is constructed by combining product data information and ATE control information. An architecture utilizing expanded PDI is designed, which enables the engineer to conduct statistical approach investigation and reduce the setup time, as well as increase yield.

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Derating design approach of aluminum electrolytic capacitor for reliability improvement (알루미늄 전해 커패시터의 신뢰성 향상을 위한 Derating 설계 연구)

  • Min, Dae-June;Kim, Jae-Jung;Son, Young-Kap;Chang, Seog-Weon;Kwack, Kae-Dal
    • Proceedings of the KSME Conference
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    • 2007.05a
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    • pp.1712-1717
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    • 2007
  • This paper presents a derating design approach for reliability improvement of an aluminum electrolytic capacitor. The capacitor, usually mounted in a printed circuit board, is used to stabilize the circuit. The main failure mechanism of interest is dry-up of the electrolyte that is mainly caused by two stresses-temperature and voltage. The lifetime under these stresses is modeled as a function of these stresses and time using accelerated life testing. Quantitative variation in the lifetime, according to variations in these stresses, is investigated to perform the derating design of the capacitor so that the stress levels are selected to achieve required reliability measures for reliability improvement. Moreover, sensitivity analysis shows which stress would be a more important factor determining the lifetime.

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Performance verification and improvement of the frequency analysis unit for GIS Preventive & Diagnostic Monitoring System (GIS 예방진단시스템 주파수 분석장치 성능개선 및 검증)

  • Kim, Won-Gyu;Kim, Min-Soo;Baek, Young-Sik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.64 no.3
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    • pp.485-491
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    • 2015
  • This paper shows the design improvement and test model of FAU (Frequency Analysis Unit) in PDD (Partial Discharge Diagnosis system) for 800kV GIS (Gas Insulated Switchgear). We found some problems during operation of previous FAU, such as the aging of fiber-optic converter that can cause communication error, the malfunction of signal analysis circuit etc. And then we solved those problems by design improvement and verified the performance through type test. To monitor partial discharge, the performance of UHF sensor is important but the performance of frequency analysis unit is also very important. So we solved communication error, the malfunction of signal analysis circuit and then increased the operation reliability of FAU by improving fiber-optic converter and signal analysis circuit. Accredited testing laboratory carried out the performance verification test according to performance test criteria and procedure of reliability test standards, IEC-60225, 61000 and 60068 etc. We confirmed the test results which correspond with the performance test criteria.

An Improvement on Testability Analysis by Considering Signal Correlation (신호선의 상관관계를 고려한 개선된 테스트용이도 분석 알고리즘)

  • 김윤홍
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.4 no.1
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    • pp.7-12
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    • 2003
  • The purpose of testability analysis is to estimate the difficulty of testing a stuck-at fault in logic circuits. A good testability measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Conventional testability measurements, such as COP and SCOAP, can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy is due to the ignorance of signal correlations for making the testability analysis linear to a circuit size. This paper proposes an efficient method for computing testability analysis, which takes into account signal correlation to obtain more accurate testability. The proposed method includes the algorithm for identifying all reconvergent fanouts in a given n circuit and the gates reachable from them, by which information related to signal correlation is gathered.

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Development of an Improved RF Dosimeter (개량된 비접촉형 RF 선량계 구현)

  • Son, Jong-Dea;Lee, Seung-Min;Lee, Heung-Ho;Lee, Nam-Ho;Lee, Seung-Ho
    • Proceedings of the KIEE Conference
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    • 2003.11c
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    • pp.540-543
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    • 2003
  • This paper presents design and manufacture of RF type non-contact radiological dosage measuring device. It also concerns on the broad out-line and the ways of improvement about RF type non-contact radiation measuring device. Measuring radiological dosage with non-contact RF, the stability and efficiency of the measure have been improved by reforming constant current circuit. Furthermore, applying communication protocol in process makes it possible to achieve faster and more accurate communication than old circuit. On the base of those, RF type non-contact radiological dosage measuring device which consists of radiological dosage measuring module and Reader module has been designed and manufactured. While testing communication against embodied device, the possibility of the field application could be confirmed.

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Piezoelectric Vibration Energy Harvester Using Indirect Impact (간접 충격을 이용한 압전 방식 진동형 에너지 하베스터)

  • Ju, Suna;Ji, Chang-Hyeon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.66 no.10
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    • pp.1499-1507
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    • 2017
  • This paper presents an impact-based piezoelectric vibration energy harvester using a freely movable metal sphere and a piezoceramic fiber-based MFC (Macro Fiber Composite) as piezoelectric cantilever. The free motion of the metal sphere, which impacts both ends of the cavity in an aluminum housing, generates power across a cantilever-type MFC beam in response to low frequency vibration such as human-body-induced motion. Impacting force of the spherical proof mass is transformed into the vibration of the piezoelectric cantilever indirectly via the aluminum housing. A proof-of-concept energy harvesting device has been fabricated and tested. Effect of the indirect impact-based system has been tested and compared with the direct impact-based counterpart. Maximum peak-to-peak open circuit voltage of 39.8V and average power of $598.9{\mu}W$ have been obtained at 3g acceleration at 18Hz. Long-term reliability of the fabricated device has been verified by cyclic testing. For the improvement of output performance and reliability, various devices have been tested and compared. Using device fabricated with anodized aluminum housing, maximum peak-to-peak open-circuit voltage of 34.4V and average power of $372.8{\mu}W$ have been obtained at 3g excitation at 20Hz. In terms of reliability, housing with 0.5mm-thick steel plate and anodized aluminum gave improved results with reduced power reduction during initial phase of the cyclic testing.

The Performance Improvement of Lightning Arrester Leakage Current Measuring Device for GIS (GIS용 피뢰기 누설전류 측정장치 성능개선)

  • Kim, Won-Gyu;Kim, Min-Soo;Baek, Young-Sik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.63 no.12
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    • pp.1726-1731
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    • 2014
  • This paper shows the developed new lightning arrester LCM (Leakage Current Measuring device) which is important element of GIS (Gas Insulated Switchgear) Preventive & Diagnostic system and verify its performance though strengthened test standards. The existing lightning arrester LCM was modified to solve measuring errors which happened frequently. At first, we explained the principle of measuring leakage current. Through analyzing some problems which the existing LCM have. we got some improvable items. For the performance verification of the improved LCM, we manufactured prototype LCM which is applied some improvable items such as improving LCM circuit, adding protection circuit, optimizing inner structure of LCM and changing ground design. After then we carried out the performance test. Accredited testing laboratory carried out the performance verification test according to performance test criteria and procedure of reliability test standards, IEC-60225, 61000 and 60068 etc. We confirmed the test results which correspond with the performance test criteria. Also, we confirmed the performance of the improved LCM installed & being operated at G Substation through the immunity test against the normal noise and open/close surge etc.