• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.771-777
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• 2012

This paper proposes a binary arithmetic encoder of CABAC using a Common Operation Unit including the three modes. The binary arithmetic encoder performing arithmetic encoding and renormalizer can be simply implemented into a hardware architecture since the COU is used regardless of the modes. The proposed binary arithmetic encoder of CABAC includes Context RAM, Context Updater, Common Operation Unit and Bit-Gen. The architecture consists of 4-stage pipeline operating one symbol for each clock cycle. The area of proposed binary arithmetic encoder of CABAC is reduced up to 47%, the performance of proposed binary arithmetic encoder of CABAC is 19% higher than the previous architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1203-1212
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• 2013

In this paper, an intra prediction hardware architecture is proposed to reduce computational complexity of intra prediction in HEVC decoder. The architecture uses shared operation units and common operation units and adopts a fast smoothing decision algorithm and a fast algorithm to generate coefficients of a filter. The shared operation unit shares adders processing common equations to remove the computational redundancy. The unit computes an average value in DC mode for reducing the number of execution cycles in DC mode. In order to reduce operation units, the common operation unit uses one operation unit generating predicted pixels and filtered pixels in all prediction modes. In order to reduce processing time and operators, the decision algorithm uses only bit-comparators and the fast algorithm uses LUT instead of multiplication operators. The proposed architecture using four shared operation units and eight common operation units which can reduce execution cycles of intra prediction. The architecture is synthesized using TSMC 0.13um CMOS technology. The gate count and the maximum operating frequency are 40.5k and 164MHz, respectively. As the result of measuring the performance of the proposed architecture using the extracted data from HM 7.1, the execution cycle of the architecture is about 93.7% less than the previous design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2503-2510
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• 2012

This paper proposes a parallel operation intra predictor for H.264/AVC decoder. In previous intra predictor design, common operation units were designed for 17 prediction modes in order to compute more effectively. However, it was designed by analyzing the equation applied to one pixel. So, there are four operation units for computing 16 pixels in a $4{\times}4$ block and they need four cycles. In this paper, the proposed intra predictor contains T3(Three Type Transform) operation unit for parallel operation. It divides 17 modes into 3 types to calculate 16 pixels of a $4{\times}4$ block in only one cycle and needs 16 cycles minimum in 16x16 block. As the result of the experiment, in terms of processing cycle, the performance of proposed intra predictor is 58.95% higher than the previous one.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.1-7
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• 2011

Active power control scheme for distributed generation in microgrid consists of feeder flow control and unit power control. Feeder flow control is more useful than the unit power control for demand-side management, because microgrid can be treated as a dispatchable load at the point of common coupling(PCC). This paper presents detailed descriptions of the feeder flow control scheme for the hybrid system in microgrid. It is divided into three parts, namely, the setting of feeder flow reference range for stable hybrid system operation, feeder flow control algorithm depending on load change in microgrid and hysteresis control. Simulation results using the PSCAD/EMTDC are presented to validate the inverter control method for a feeder flow control mode. As a result, the feeder flow control algorithm for the hybrid system in microgrid is efficient for supplying continuously active power to customers without interruption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2253-2260
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• 2012

In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.3
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• pp.87-94
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• 2013

The main purpose of the distribution automation system (DAS) is to achieve efficient operation of primary distribution systems by monitoring and control of the feeder remote terminal unit(FRTU) deployed on the distribution feeders. DAS simulators are introduced to verify the functions of the application software installed in the central control unit(CCU) of the DAS. Because each DAS is developed on the basis of its own specific data model, the power system data cannot be easily transferred from the DAS to the simulator or vice versa. This paper presents a common information model(CIM)-based DAS simulator to achieve interoperability between the simulator and the DASs developed by different vendors. The CIM-based data model conversion between Smart DMS (SDMS) and Total DAS (TDAS) has been performed to establish feasibility of the proposed scheme.

• Journal of Korean Society of Transportation
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• v.33 no.3
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• pp.237-246
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• 2015

Operation and Maintenance in road infrastructure is repetitive carbon emissions activities to preserve the road in its originally constructed condition. In the view of road planning and construction, operation, and maintenance of life cycle, operation and maintenance stage quantification of carbon emissions is very important because it is easily accessible activities to reduce carbon emissions in road infrastructure that existing and new road. However, carbon emissions estimation in operation and maintenance stage is yet to do, because data collection is so hard and carbon emissions estimation methodology is very complicated. In this study, a basic unit of carbon emission in the operation and maintenance stage of the road infrastructure was developed in order to get the quantitative determination of carbon that occurring. Carbon emissions of the Expressway and Common state road was calculated by using the basic unit of carbon emission and application plan of basic unit of carbon emission are presented.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• The Korean Journal of Archival Studies
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• no.70
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• pp.85-117
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• 2021

The purpose of this study is to investigate and analyze the current status of unit tasks, unit task operation, and record management problems used by local governments, and to present improvement measures using text-based big data technology based on the implications derived from the process. Local governments are in a serious state of record management operation due to errors in preservation period due to misclassification of unit tasks, inability to identify types of overcommon and institutional affairs, errors in unit tasks, errors in name, referenceable standards, and tools. However, the number of unit tasks is about 720,000, which cannot be effectively controlled due to excessive quantities, and thus strict and controllable tools and standards are needed. In order to solve these problems, this study developed a system that applies text-based analysis tools such as corpus and tokenization technology during big data analysis, and applied them to the names and construction terms constituting the record management standard. These unit task operation support tools are expected to contribute significantly to record management tasks as they can support standard operability such as uniform preservation period, identification of delegated office records, control of duplicate and similar unit task creation, and common tasks. Therefore, if the big data analysis methodology can be linked to BRM and RMS in the future, it is expected that the quality of the record management standard work will increase.