• Journal of Information Processing Systems
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• v.18 no.2
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• pp.188-196
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• 2022

Recently, neural architecture search (NAS) has received increasing attention as it can replace human experts in designing the architecture of neural networks for different tasks and has achieved remarkable results in many challenging tasks. In this study, a path-based computation neural architecture encoder (PCE) was proposed. Our PCE first encodes the computation of information on each path in a neural network, and then aggregates the encodings on all paths together through an attention mechanism, simulating the process of information computation along paths in a neural network and encoding the computation on the neural network instead of the structure of the graph, which is more consistent with the computational properties of neural networks. We performed an extensive comparison with eight encoding methods on two commonly used NAS search spaces (NAS-Bench-101 and NAS-Bench-201), which included a comparison of the predictive capabilities of performance predictors and search capabilities based on two search strategies (reinforcement learning-based and Bayesian optimization-based) when equipped with different encoders. Experimental evaluation shows that PCE is an efficient encoding method that effectively ranks and predicts neural architecture performance, thereby improving the search efficiency of neural architectures.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.22-32
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• 1997

This paper proposes an imprecise compuitation model for DCT considering QOS of images and a two dimensional DCT architecture for imprecise computations. In case that many processes are scheduling in a hard real time system, the system resources are shared among them. Thus all processes can not be allocated enough system resources (such as processing power and communication bandwidth). The imprecise computtion model can be used to provide scheduling flexibility and various QOS(quality of service)levels, to enhance fault tolerance, and to ensure service continuity in rela time systems. The DCT(discrete cosine transform) is known as one of popular image data compression techniques and adopted in JPEG and MPEG algorithms since the DCT can remove the spatial redundancy of 2-D image data efficiently. Even though many commercial data compression VLSI chips include the DCST hardware, the DCT computation is still a very time-consuming process and a lot of hardware resources are required for the DCT implementation. In this paper the DCT procedure is re-analyzed to fit to imprecise computation model. The test image is simulated on teh base of this model, and the computation time and the quality of restored image are studied. The row-column algorithm is used ot fit the proposed imprecise computation DCT which supports pipeline operatiions by pixel unit, various QOS levels and low speed stroage devices. The architecture has reduced I/O bandwidth which could make its implementation feasible in VLSI. The architecture is proved using a VHDL simulator in architecture level.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.6
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• pp.2202-2206
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• 2010

In this paper, an architecture for modified Euclidean(ME) algorithm is proposed, which is using finite-state machine(FSM) instead of degree computation. Since the proposed architecture does not have degree computation circuits, it is possible to reduce the hardware complexity of RS(Reed-Solomon) decoder, so that a very high-speed RS decoder can be implemented. RS(255,239) decoder with the proposed architecture is implemented using Verilog-HDL and requires about 13% fewer gate counts than conventional one.

• Journal of Internet Computing and Services
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• v.19 no.2
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• pp.33-41
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• 2018

In recent years, technology is rapidly changing to support new service consumption and distribution models in multimedia service systems and hybrid delivery of media services is a key factor for enabling next generation multimedia services. This phenomenon can lead to rapidly increasing network traffic and ultimately has a direct and aggravating effect on the user's quality of service (QOS). To address the issue, we propose a novel system architecture to provide smart hybrid media services efficiently. The architecture is designed to apply the software-defined networking (SDN) method, detect changes in traffic, and combine the data, including user data, service features, and computation node status, to provide a service schedule that is suitable for the current state. To this end, the proposed architecture is based on 2-level scheduling, where Level-1 scheduling is responsible for the best network path and a computation node for processing the user request, whereas Level-2 scheduling deals with individual service requests that arrived at the computation node. This paper describes the overall concept of the architecture, as well as the functions of each component. In addition, this paper describes potential scenarios that demonstrate how this architecture could provide services more efficiently than current media-service architectures.

• Convergence Security Journal
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• v.13 no.6
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• pp.3-9
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• 2013

With the rapidly changing information communication environment and development of technologies, the informati on networks are evolved from traditional fixed form to an active variable network that flexible large variety of data can be transferred. To reflect the needs of users, the next generation using DWDM (Dense Wavelength Division M ultiplexing) transmission system and OXC (Optical Cross Connect) form a dynamic network. After that GMPLS (Ge neralized Multi-Protocol Label Switching) can be introduced to dynamically manage and control the Reconfigurable Optical Add-drop Multiplexer (ROADM)/Photonic Cross Connect (PXC) based network. This paper propose a softw are architecture of Path Computation Element (PCE) protocol that has proposed by Internet Engineering Task Force (IETF) to path computation. The functional blocks and Application Programming Interface (API) of the PCE protoco l implementation are also presented.

• Convergence Security Journal
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• v.13 no.4
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• pp.19-25
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• 2013

The increasing demand for fast, flexible and guaranteed Quality of Service (QoS) in core networks has caused to deploy MultiProtocol Label Switching (MPLS) and Generalized MPLS (GMPLS) control plane. In GMPLS control plane, path computation and cooperation processes are one of the crucial element to maintain an acceptable level of service. The Internet Engineering Task Force (IETF) has proposed the Path Computation Element (PCE) architecture. The PCE is a dedicated network element devoted to path computation process and communications between Path Computation Clients (PCC) and PCEs is realized through the PCE Protocol (PCEP). This paper examines the PCE-based path computation architecture to include the design and implementation of PCEP. The functional modules including Finite State Machine (FSM) and related key design issues of each state are presented. In particular we also discuss internal/external protocol interfaces that efficiently control the communication channels.

• International Journal of Naval Architecture and Ocean Engineering
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• v.12 no.1
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• pp.146-156
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• 2020

Two High Tensile Strength Steel (EH47) plates with thickness of 70 mm were butt-welded together by multi-pass Submerged Arc Welding (SAW), also the hardness and welding residual stress were investigated experimentally. Based on Thermal-Elastic-Plastic Finite Element (TEP FE) computation, the thermal cycles during entire welding process were obtained, and the HAZ hardness of multi-pass butt welded joint was computed by the hardenability algorithm with considering microstructure evolution. Good agreement of HAZ hardness between the measurement and computational result is observed. The evolution of each phase was drawn to clarify the influence mechanism of thermal cycle on HAZ hardness. Welding residual stress was predicted with considering mechanical response, which was dominantly determined by last cap welds through analyzing its formation process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1902-1918
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• 1993

Parallel architecture based on the von Neumann computation model has a limitation as a massively parallel architecture due to its inherent drawback of architectural features. The data-flow model of computation has a high programmability in software perspective and high scalability in hardware perspective. However, the practical programming and experimentaion of date-flow architectures are hardly available due to the absence of practical data-flow, we present a programming environment for performing the data-flow computation on conventional parallel machines in general, loosely compled multiprocessor system in particular. We build an emulator for tagged token data-flow architecture on the iPSC/2 hypercube, a loosely coupled multiprocessor system. The emulator is a shallow layer of software executing on an iPSC/2 system, and thus makes the iPSC/2 system work as a data-flow architecture from the programmer`s viewpoint. We implement various numerical and non-numerical algorithm in a data-flow assembler language, and then compare the performance of the program with those of the versions of conventional C language, Consequently, We verify the effectiveness of this programming environment based on the emulator in experimenting the data-flow computation on a conventional parallel machine.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6C
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• pp.603-613
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• 2006

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of Power consumption is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7\sim8%$ without compromising the final DCT results. The proposed low-power DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.57-64
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• 2006

Multiprocessor system on chip (MPSoC) platforms has set a new innovative trend for the SoC design. Quality of service parameters and performance matrix are leading to the adoption of new design methodology for SoC, which will incorporate highly scalable, reusable, predictable, cost and energy efficient platform not only for underlying communication backbone but also for the entire system architecture of NOC. Like the layered architecture for the communication backbone of NOC, we have proposed the entire system architecture for NOC to be a seven layered architecture in itself. Such a platform can separate the domain specific issues which will model concurrency along with the synchronization issues more effectively. For such a layered architecture, model of computation will provide a framework to that can model concurrency and synchronization issues which are natural for any application. Therefore it becomes extremely important to use a right computation model in a specific NOC region.