• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.53-57
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• 2017

This paper proposes a 401MHz-406MHz low noise amplifier for MedRadio applications. The proposed low noise amplifier adopts a common gate amplifier topology using current reuse gm-boosting technique. The proposed low noise amplifier shows better performance of voltage gain and noise figure than the conventional gm-boosted common gate amplifier in the same power consumption. The proposed current-reuse gm-boosted low noise amplifier achieves a voltage gain of 22 dB, a noise figure of 2.95 dB, and IIP3 of -17 dBm while consuming $170{\mu}W$ from a 0.5 V supply voltage in $0.13{\mu}m$ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1465-1470
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC $0.18{\mu}m$ CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.30-40
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• 2002

A 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard $0.35\mu\textrm$ CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.

• Proceedings of the Korea Concrete Institute Conference
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• 2000.10b
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• pp.1079-1084
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• 2000

The apartment houses which were constructed in a large quantity are currently being deteriorated and the reuse of them is directly related to the economic and environmental problem of the nation. Therefore, this research approaches to structural planning other than to the materials and/or the repair for the reuse of these deteriorated buildings. The research suggests the structural planning technique which includes the idea for the reinforcement of the structure in a part to improve the structural efficiency by investigating the current condition which includes the structural type of the buildings, examining the plan for the improvement of the structural efficiency, establishing the model of the space reorganization associated to the capability changes for the scale, the use, and the facilities, and checking of the structural efficiency through the structural analysis for the building structure suggested to be replaced.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.4
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• pp.217-228
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• 2022

Currently, there are increasing demands for applying deep neural networks (DNNs) in the embedded domain such as classification and object detection. The DNN processing in embedded domain often requires custom hardware such as NPU for acceleration due to the constraints in power, performance, and area. Processing DNN models requires a large amount of data, and its seamless transfer to NPU is crucial for performance. In this paper, we developed a cycle-accurate NPU simulator to evaluate diverse NPU microarchitectures. In addition, we propose a novel technique for reducing the number of memory accesses when processing convolutional layers in convolutional neural networks (CNNs) on the NPU. The main idea is to reuse data with memory interleaving, which recycles the overlapping data between previous and current input windows. Data memory interleaving makes it possible to quickly read consecutive data in unaligned locations. We implemented the proposed technique to the cycle-accurate NPU simulator and measured the performance with LeNet-5, VGGNet-16, and ResNet-50. The experiment shows up to 2.08x speedup in processing one convolutional layer, compared to the baseline.

• The Journal of the Convergence on Culture Technology
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• v.9 no.3
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• pp.835-843
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• 2023

Given the structure of XML data, path and tree pattern matching algorithms play an important role in XML query processing. To facilitate decisions or relationships between nodes, nodes in an XML tree are typically labeled in a way that can quickly establish an ancestor-descendant on relationship between two nodes. However, these techniques have the disadvantage of re-labeling existing nodes or recalculating certain values if insertion occurs due to sequential updates. Therefore, in current labeling techniques, the cost of updating labels is very high. In this paper, we propose a new labeling technique called Fast XML encoding, which supports the update of order-sensitive XML documents without re-labeling or recalculation. It also controls the length of the label by reusing deleted labels at the same location in the XML tree. The proposed reuse algorithm can reduce the length of the label when all deleted labels are inserted in the same location. The proposed technique in the experimental results can efficiently handle order-sensitive queries and updates.

• Journal of Korea Multimedia Society
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• v.9 no.6
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• pp.750-761
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• 2006

As CBD technologies and researches have been matured, component framework as a larger reuse unit than component is being introduced. Especially issues related with adaptation and integration of components in CBD are being raised as a new research topic. The component framework is given as a solution to resolve these issues. However, current approaches don't suggest a sound and comprehensive reference model and development process applying reference model. In order to develop practical and stable component framework, reference model and concrete guidelines are essential elements. In this paper, we propose a generic reference model integrating existing reference models and a design technique of component framework based on it. Especially, we propose concrete and pragmatic guidelines such as how to design component framework architecture's view and style, how to design commonality and variability of component framework, how to design macro workflows among components, and so on. We believe that the proposed reference model becomes basis for component framework development, and the proposed design technique will support reliable and effective development of the component framework.

• Journal of Engineering Education Research
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• v.4 no.2
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• pp.27-34
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• 2001

Java Applets are major learning components in current Web-based educational system. In this paper, it is shown how Java Beans technology is applied to develop engineering Java Applets. This technique enables us to reuse the developed components and to increase the programming productivity. Also, these components are integrated into 5 different Applet types, each of which represents a good educational pattern in Applet programming. The results are applied to develop engineering class contents like Electrical Circuit theory, Engineering Mathematics, athematics, and Electrical Machine. Development times are analysed to show how this technique helped in reducing production period.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.62-66
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• 2016

This paper presents a MedRadio-band low power low noise amplifier for Medical Devices. A proposed MedRadio-band low power low noise amplifier adopts a current-reuse resistive feedback topology to increase overall gm and reduce power consumption. The gain of the LNA increases by the Q-factor of the additional series RLC input matching network, and its noise figure is minimized by the similar factor. Furthermore, it consumes low power because of low supply voltage and current reuse technique. By exploiting the $g_m$-booting and matching network property, the proposed MedRadio-band low noise amplifier achieves a noise figure of 0.85 dB, a voltage gain of 30 dB, and IIP3 of -7.9 dBm while consuming 0.18 mA from a 1 V supply voltage in $0.13{\mu}m$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.341-346
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• 2017

In this paper, we present a 60 GHz on-off keying (OOK) modulator in a 90 nm CMOS. The modulator employs a current-reuse technique and a switching modulation for low DC power dissipation, high on/off isolation, and high data rate. The measured gain of the modulator, on/off isolation, and output 1-dB compression point is 9.1 dB, 24.3 dB, and 5.1 dBm, respectively, at 60 GHz. The modulator consumes power consumption of 18 mW, and is capable of handling data rates of 8 Gb/s at bit error rate of less than $10^{-6}$ for $231^{-1}$ PRBS over a distance of 10-cm with an OOK receiver module.