• Journal of Advanced Navigation Technology
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• v.13 no.5
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• pp.684-690
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• 2009

In this paper, we propose the acceleration method of the DDR-SSD RAID level 5. The DDR-SSD is the storage device of the Next Generation Storage(NGS) system. The DDR-SSD has different characteristics with HDD and Flash SSD. That's why the DDR-SSD RAID level 5 does not provide the best performance when the normal acceleration method is used. In this paper, to accelerate the DDR-SSD RAID level 5 operation, we propose the parity cache and the architecture of the parity cell. The parity cache stores only parity blocks. This acceleration method proposed in this paper reduce the number of the disk access and the overhead of parity operations.

• Journal of Advanced Navigation Technology
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• v.14 no.5
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• pp.752-759
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• 2010

In this paper, we propose differential-logging method to improve the performance of RMW(Read Modify Write) operations of DDR-SSD based software RAID. Small writes that are frequently occurred in enterprise applications are main factor to degrade the performance of RAID5. Once a block is updated in RAID5, the parity block of the block must be updated to maintain consistency of parity. Therefore, to process a small write request, we need to read its parity block stored in disk, read old data, perform XOR operation, and write updated data and parity block. Several methods for hard disk based software RAID are proposed to solve the small write problems in RAID 5. Ln this paper, we propose a differential-logging method which carefully considers the DDR-SSD to solve the small write problem in RAID 5. We show that our proposed method out performs the existing software RAID in LINUX through simulations.

• Journal of Advanced Navigation Technology
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• v.13 no.4
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• pp.509-514
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• 2009

In this paper, we designed and analyzed 256GB DRAM-based SSD storage using DDR1 memory and PCI-e interface. SSD is a storage system that uses DRAM or NAND Flash as primary storage media. Since the SSD read and write data directly to memory chips, which results in storage speeds far greater than conventional magnetic storage devices, HDD. Architecture of the proposed SSD system has performance of high speed data processing duo to use multiple RAM disks as primary storage and PCI-e interface bus as communication path of RAM disks. We constructed experimental system with UNIX, Windows/Linux server, SAN Switch, and Ethernet Switch and measured IOPS and bandwidth of proposed SSD using IOmeter. In experimental results, it has been shown that IOPS, 470,000 and bandwidth,800MB/sec of the DDR-1 SSD is better than those of the HDD and Flash-based SSD.

• ETRI Journal
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• v.44 no.3
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• pp.450-461
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• 2022

The Gen-Z protocol is a memory semantic protocol between the memory and CPU used in computer architectures with large memory pools. This study presents the implementation of the Gen-Z hardware system configured using Gen-Z specification 1.0 and reports its performance. A hardware prototype of a DDR4 Gen-Z memory pool with an optimized character, a block device driver, and a file system for the Gen-Z hardware was designed. The Gen-Z IP was targeted to the FPGA, and a 512 GB Gen-Z memory pool was configured on an ×86 server. In the experiments, the latency and throughput of the Gen-Z memory were measured and compared with those of the local memory, SATA SSD, and NVMe using character or block device interfaces. The Gen-Z hardware exhibited superior throughput and latency performance compared with SATA SSD and NVMe at block sizes under 4 kB. The MySQL and File IO benchmark of Gen-Z showed good write performance in all block sizes and threads. Besides, it showed low latency in RocksDB's fillseq dbbench using the ext4 direct access filesystem.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of Advanced Navigation Technology
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• v.13 no.6
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• pp.957-963
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• 2009

It is necessary for the resource management system to manage for the resource in distributed networking environment. Because of increasing the complexity of vast computer system and business environment, needs of RMS is increasing. Based on the common information model to use of objected oriented technology, through analysis of the reference model for the resource management system of the SNIA, we intend to implement the application program to manage the NGS system that consist of SSD and DRAM. To visualize, it is use the GUI Interface. It is possible for application program(Client) to detect and manage the system that consist of the NGS system. Also, status information that is divided into three cataloges(Minor/Major/Critical) can be displayed and it provide support of configuration functionality to manage devices.

• Journal of Advanced Navigation Technology
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• v.14 no.5
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• pp.767-774
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• 2010

Due to advantages of NAND flash memory such as non-volatility, low access latency, low energy consumption, light weight, small size and shock resistance, it has become a better alternative over traditional magnetic disk drives, and has been widely used. Traditional DBMSs including mobile DBMSs may run on flash memory without any modification by using Flash Translation Layer (FTL), which emulates a random access block device to hide the characteristics of flash memory such as "erase-before-update". However, most existing FTLs are optimized for file systems, not for DBMSs, and traditional DBMSs are not aware of them. Also, traditional DBMSs do not consider the characteristics of flash memory. In this paper, we propose a flash-conscious storage system for DBMSs that utilizes flash memory as a main storage medium, and carefully put the characteristics of flash memory into considerations. The proposed flash-conscious storage system exploits log records to avoid costly update operations. It is shown that the proposed storage system outperforms the state.