• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.62-68
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• 1989

In this paper, Analog/Digital BCDMOS technology that the bipolar devices for driver applications CMOS devices for logic applications, and DMOS devices for high voltage applications is pressented. An optimized poly-gate p-well CMOS process is chosen to fabricate the BCDMOS, and the basic concepts to desigh these devices are to improve the characteristics of bipolar, CMOS & DMOS with simple process technology. As the results, $h_{FE}$ value is 320 (Ib-$10{\mu}A$ for bipolar npn transistor, and there is no short channel effects for CMOS devices which have Leff to $1.25{\mu}m$ and $1.35{\mu}m$ for n-channel and p-channel, respectively. Finally, breakdown voltage is obtained higher than 115V for DMOS device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.696-698
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• 2012

This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generate about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1286-1293
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• 1988

A general closed form expression for the channel length of the self-aligned double-diffused MOS transistor is obtained from the 2-dimensional Gaussian doping profile. The proposed model in this paper is composed of the doping concentration of the substrate, the final surface doping concentration and the vertical junction depth of the each double-diffused region. The calculated channel length is in good agreement with the experimental results. Also, the optimum channel structure for the prevention of the channel puncthrough is obtained by the averaged doping concentration in the channel region. A correspondence between the results of device simulation of channel punchthrough and the estimations of simplified model is confirmed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1741-1746
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• 2012

This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generates about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.13-18
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• 2007

This paper presents the experimental findings on the different degradation mechanism which depends on the gate oxide thickness in lateral DMOS transistors. For thin oxide devices, the generation of interface states in the channel region and the trapped holes in the drift region is found to be the causes of the device degradation. For thick devices, the generation of interface states in the channel region is found to be the causes of the device degradation. We confirmed the different degradation mechanism using device simulation. From the comparison of device degradation under DC and AC stress, it is found that the device degradation is more significant under DC stress than one under AC stress. The device degradation under AC stress is more significant in high frequency. Therefore the hot carrier induced degradation should be more carefully considered in the design of RF LDMOS transistors and circuit design.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.2
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• pp.116-119
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• 2000

A hybrid SOI bipolar-mode field effect transistor (BMFET) is proposed to improve the current gain. The device characteristics are analyzed and verified numerically for BMFET mode, DMOS mode, and hybrid mode by MEDICI simulation. The proposed SOI BMFET exhibits 30 times larger current gain in hybrid-mode operation by connecting DMOS gate to the p+ gate of BMFET structure as compared with the conventional structure without sacrifice of breakdown voltage and leakage current characteristics. This is due to the DMOS-gate-induced hybrid effect that lowers the barrier of p-body and reduces the charge in p-body.

• Journal of IKEEE
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• v.20 no.4
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• pp.428-431
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• 2016

Power semiconductor devices had been producted with bipolar only processes, but Bipolar-CMOS-DMOS(BCD) processes have been adapted recently to fabricate these devices since most foundry companies have provided BCD processes instead of Bipolar only processes. In this study, Regulator and OP Amp are used as most popular design IPs and BCD processes for the designing are converted from bipolar only processes. Power Switching Sensor(PSS) ICs are designed specifically and fabricated on a silicon chip. The operation results of the packaged chip show the good matching with test results of the simulation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.6
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• pp.2464-2479
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• 2020

This paper presents a detailed subjective quality assessment for the ultra-high definition (UHD) videos having frame rates of 30fps and 60 fps. The subjective assessment is based on the ITU-R BT-500 recommendations, where double stimulus continuous quality scale (DSCQS-type II) test is performed for the evaluation of the perceived quality of the user's in terms of differential mean opinion score (DMOS). Encoding of the UHD videos by opting encoders i.e. H.264/AVC, H.265/HEVC, and VP9 at five different quantization parameter (QP) levels is done to investigate the perceived user's quality of experience (QoE) given as DMOS. Moreover, the encoding efficiency as the encoding time for each encoder and qualitative performance by employing full-reference (FR) quality metrics are presented in this work.

• Phonetics and Speech Sciences
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• v.2 no.1
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• pp.71-75
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• 2010

The PESQ is an objective speech quality evaluation measure that is known to have a high correlation with a subjective speech quality measure such as MOS. To examine whether it could be useful as an objective quality measure of synthetic speech, we carried out both subjective evaluation tests with MOS and DMOS and an objective evaluation test with PESQ for HMM-based Korean synthetic speech signals and analyzed the correlation between them. Experimental results have shown that the PESQ has correlations of 0.87 with MOS and 0.92 with DMOS. It means that the PESQ holds much promise for evaluating the quality of synthetic Korean speech.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.9
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• pp.523-526
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• 2000

A dual gate trench emitter IGBT structure is proposed and studied numerically using the device simulator MEDICI. The on-state forward voltage drop latch-up current density turn-off time and breakdown voltage of the proposed structure are compared with those of the conventional DMOS-IGBT and trench gate IGBT structures. The proposed structure forms an additional channel and increases collector current level resulting in reduction of on -state forward voltage drop. In addition the trench emitter increases latch-up current density by 148% in comparison with that for the conventional DMOS-IGBT and by 83% compared with that for the trench gate IGBT without degradation in breakdown voltage when the half trench gate width(Tgw) and trench emitter depth(Ted) are fixed at $1.5\mum\; and\; 2\mum$, respectively