• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.599-602
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• 2014

FPGA상에 AES 복호화 코어를 FIPS-197사양에 기술된 AES 알고리즘의 복호화부분을 구현하였다. 키값의 길이는 128/192/256비트를 지원하며, 별도의 코어 로직은 FPGA의 6-input lookup table의 이점을 살리도록 설계되었으며, 이결과로 2000개의 lookup table만을 이용하여 256비트 키에서 3Gbps의 처리가 가능하게 되었다. 코어는 난수 및 FIPS-197, SP-800a와 AESAVS사양의 테스트 벡터를 통해서 검증하였다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.