• 산업경영시스템학회지
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• 제46권2호
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• pp.1-12
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• 2023

To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.

• 산업공학
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• 제17권1호
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• pp.1-12
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• 2004

In a modern semiconductor device manufacturing industry, statistical bin limits on wafer level test bin data are used for minimizing value added to defective product as well as protecting end customers from potential quality and reliability excursion. Most wafer level test bin data show skewed distributions. By Monte Carlo simulation, this paper evaluates methods and sample size effect regarding determination of statistical bin limits. In the simulation, it is assumed that wafer level test bin data follow the Poisson distribution. Hence, typical shapes of the data distribution can be specified in terms of the distribution's parameter. This study examines three different methods; 1) percentile based methodology; 2) data transformation; and 3) Poisson model fitting. The mean square error is adopted as a performance measure for each simulation scenario. Then, a case study is presented. Results show that the percentile and transformation based methods give more stable statistical bin limits associated with the real dataset. However, with highly skewed distributions, the transformation based method should be used with caution in determining statistical bin limits. When the data are well fitted to a certain probability distribution, the model fitting approach can be used in the determination. As for the sample size effect, the mean square error seems to reduce exponentially according to the sample size.

• 응용통계연구
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• 제35권5호
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• pp.593-601
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• 2022

빈번하지는 않지만 한번 발생하면 상대적으로 큰 손실을 가져오는 사례를 통칭하여 부정 사례(Fraud)라고 부르며, 부정 탐지의 문제는 많은 분야에서 활용된다. 부정 사례는 정상 사례에 비해 상대적으로 관측치가 매우 적고 오분류의 비용이 월등히 크기 때문에 일반적인 이항분류 기법을 바로 적용할 수 없다. 이러한 경우에 활용할 수 있는 방법이 부정 탐지 지지 벡터기계(FDSVM)이다. 본 논문에서는 공변량이 함수형일 때 활용 가능한 함수형 부정 탐지 지지 벡터기계(F²DSVM)를 제안하였다. 제안된 방법을 사용하면 함수형 공변량을 가진 데이터에서 사용자가 목표하는 부정 탐지의 성능을 만족시키는 제약하에서 최적의 예측력을 가지는 분류기를 학습시킬 수 있다. 뿐만아니라, 통상적인 SVM과 마찬가지로, F²DSVM도 자취해의 조각별 선형성을 보일 수 있으며 이를 바탕으로 효율적인 자취해 알고리즘을 활용할 수 있고 분류기의 학습 시간을 크게 단축시킬 수 있다. 마지막으로, 반도체 웨이퍼 불량 탐지 문제에 제안된 F²DSVM을 적용해 보았고, 그 활용 가능성을 확인하였다.

• 응용통계연구
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• 제35권3호
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• pp.407-419
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• 2022

반도체는 제조 공정이 복잡하고 길어 결함이 발생될 때 빠른 탐지와 조치가 이뤄져야 결함으로 인한 손실을 최소화할 수 있다. 테스트 공정을 거쳐 구성된 웨이퍼 빈 맵(WBM)의 체계적인 패턴을 탐지하고 분류함으로써 문제의 원인을 유추할 수 있다. 이 작업은 수작업으로 이뤄지기 때문에 대량의 웨이퍼를 단 시간에 처리하는 데 한계가 있다. 본 논문은 웨이퍼 빈 맵의 정상 여부를 구분하기 위해 계층적 군집 분석을 활용한 새로운 결함 패턴 탐지 방법을 제시한다. 제시하는 방법은 여러 장점이 있다. 군집의 수를 알 필요가 없으며 군집분석의 조율 모수가 적고 직관적이다. 동일한 크기의 웨이퍼와 다이(die)에서는 동일한 조율 모수를 가지므로 대량의 웨이퍼도 빠르게 결함을 탐지할 수 있다. 소량의 결함 데이터만 있어도 그리고 데이터의 결함비율을 가정하지 않더라도 기계학습 모형을 훈련할 수 있다. 제조 특성상 결함 데이터는 구하기 어렵고 결함의 비율이 수시로 바뀔 수 있기 때문에 필요하다. 또한 신규 패턴 발생시에도 안정적으로 탐지한다. 대만 반도체 기업에서 공개한 실제 웨이퍼 빈 맵 데이터(WM-811K)로 실험하였다. 계층적 군집 분석을 이용한 결함 패턴탐지는 불량의 재현율이 96.31%로 기존의 공간 필터(spatial filter)보다 우수함을 보여준다. 결함 분류는 혼합 유형에 장점이 있는 계층적 군집 분석을 그대로 사용한다. 직선형과 곡선형의 긁힘(scratch) 결함의 특징에 각각 주성분 분석의 고유값과 2차 다항식의 결정계수를 이용하고 랜덤 포레스트 분류기를 이용한다.

• 산업경영시스템학회지
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• 제44권4호
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• pp.128-135
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• 2021

WDM(Wavelength Division Multiplexing) is called a wavelength division multiplexing optical transmission method and is a next-generation optical transmission technology. Case company F has recently developed and sold PLC(Planar Lightwave Circuit), a key element necessary for WDM system production. Although Chinese processing companies are being used as a global outsourcing strategy to increase price competitiveness by lowering manufacturing unit prices, the average defect rate of products manufactured by Chinese processing companies is more than 50%, causing many problems. However, Chinese processing companies are trying to avoid responsibility, saying that the cause of the defect is the defective PLC Wafer provided by Company F. Therefore, in this study, the responsibility of the PLC defect is clearly identified through estimating the defect rate of PLC using the sampling inspection method, and the improvement plan for each cause of the PLC defect for PLC yeild improvement is proposed. The result of this research will greatly contribute to eliminating the controversy over providing the cause of defects between global outsourcing companies and the head office. In addition, it is expected to form a partnership with Company F and a Chinese processing company, which will serve as a cornerstone for successful global outsourcing. In the future, it is necessary to increase the reliability of the PLC yield calculation by extracting more precisely the number of defects.

• Journal of the Optical Society of Korea
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• 제19권6호
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• pp.687-694
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• 2015

A photoluminescence (PL) imaging method using a vision camera was employed to inspect InGaN/GaN quantum-well light-emitting diode (LED) epi-wafers. The PL image revealed dark spot defective regions (DSDRs) as well as a spatial map of integrated PL intensity of the epi-wafer. The Shockley-Read-Hall (SRH) nonradiative recombination coefficient increased with the size of the DSDRs. The high nonradiative recombination rates of the DSDRs resulted in degradation of the optical properties of the LED chips fabricated at the defective regions. Abnormal current-voltage characteristics with large forward leakages were also observed for LED chips with DSDRs, which could be due to parallel resistances bypassing the junction and/or tunneling through defects in the active region. It was found that the SRH nonradiative recombination process was dominant in the voltage range where the forward leakage by tunneling was observed. The results indicated that the DSDRs observed by PL imaging of LED epi-wafers were high density SRH nonradiative recombination centers which could affect the optical and electrical properties of the LED chips, and PL imaging can be an inspection method for evaluation of the epi-wafers and estimation of properties of the LED chips before fabrication.

• 한국재료학회지
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• 제20권8호
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• pp.423-428
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• 2010

This study shows the effects of deionized (DI) rinse and oxide HF wet etch processes on silicon substrate during a photolithography process. We found a fail at the wafer center after DI rinse step, called Si pits, during the fabrication of a complementary metal-oxide-semiconductor (CMOS) device. We tried to find out the mechanism of the Si pits by using the silicon wafer on CMOS fabrication and analyzing the effects of the friction charge induced by the DI rinsing. The key parameters of this experiment were revolution per minute (rpm) and time. An incubation time of above 10 sec was observed for the formation of Si pits and the rinsing time was more effective than rpm on the formation of the Si pits. The formation mechanism of the Si pits and optimized rinsing process parameters were investigated by measuring the charging level using a plasma density monitor. The DI rinse could affect the oxide substrate by a friction charging phenomenon on the photolithography process. Si pits were found to be formed on the micro structural defective site on the Si substrate under acceleration by developed and accumulated charges during DI rinsing. The optimum process conditions of DI rinse time and rpm could be established through a systematic study of various rinsing conditions.

• Korean Chemical Engineering Research
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• 제51권6호
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• pp.666-670
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• 2013

실리콘계 태양전지 제조과정에서 발생하는 불량품에서 실리콘웨이퍼를 회수하는 연구를 수행하였다. 상온($25^{\circ}C$)에서 인산용액 농도, 산성불화암모늄 농도, 킬레이트제 종류 및 농도를 변화시키면서 폐태양전지의 반사방지막 및 N층의 제거 효율을 조사하였다. 10 wt% 인산, 2.0 wt% 산성불화암모늄, 1.5 wt% Hydantoin 사용 시 제거 효율이 가장 우수 하였다. 인산농도가 증가할수록 미세입자의 표면전위가 (+)로 변하여 정전기적 인력에 의해 실리콘웨이퍼 표면에 재흡착하여 표면처리 전보다 두께가 두꺼워졌으며, 표면의 오염도도 증가하였다. 인산-산성불화암모늄-킬레이트제 용액에 의한 표면처리방법은 모든 공정이 상온에서 수행되며, 공정이 단순하고, 폐수 발생량이 적고, 표면제거 효율이 우수한 방법으로 폐 태양전지의 재활용 및 기존 RCA 세정법의 대안으로 가능성이 매우 클 것으로 판단되었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.141-141
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• 2010

The effect of thermal anneal on the characteristics of structural properties and the enhancement of luminescence and photovoltaic (PV) characteristics of silicon-rich silicon-nitride films were investigated. By using an ultra high vacuum ion beam sputtering deposition, B-doped silicon-rich silicon-nitride (SRSN) thin films, with excess silicon content of 15 at. %, on P-doped (n-type) Si substrate was fabricated, sputtering a highly B doped Si wafer with a BN chip by N plasma. In order to examine the influence of thermal anneal, films were then annealed at different temperature up to $1100^{\circ}C$ under $N_2$ environment. Raman, X-ray diffraction, and X-ray photoemission spectroscopy did not show any reliable evidence of amorphous or crystalline Si clusters allowing us concluding that nearly no Si nano-cluster could be formed through the precipitation of excess Si from SRSN matrix during thermal anneal. Instead, results of Fourier transform infrared and X-ray photoemission spectroscopy clearly indicated that defective, amorphous Si-N matrix of films was changed to be well-ordered thanks to high temperature anneal. The measurement of spectral ellipsometry in UV-visible range was carried out and we found that the optical absorption edge of film was shifted to higher energy as the anneal temperature increased as the results of thermal anneal induced formation of $Si_3N_4$-like matrix. These are consistent with the observation that higher visible photoluminescence, which is likely due to the presence of Si-N bonds, from anneals at higher temperature. Based on these films, PV cells were fabricated by the formation of front/back metal electrodes. For all cells, typical I-V characteristic of p-n diode junction was observed. We also tried to measure PV properties using a solar-simulator and confirmed successful operation of PV devices. Carrier transport mechanism depending on anneal temperature and the implication of PV cells based on SRSN films were also discussed.