• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.2
• /
• pp.320-324
• /
• 2011

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.6
• /
• pp.230-238
• /
• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
• /
• 2004.04a
• /
• pp.183-195
• /
• 2004

Photogrammetry is one of the most important sources of GIS application. Nowadays, color photos are used and camera is integrated with GPS/INS sensors. However the photos are still taken from analogue camera and scanned for digital image. For the convenient and accurate image application especially for 3D, airborne digital camera images is essential. In this paper, digital image calibration process with GPS/INS and its accuracy evaluation was presented.

• Nuclear Engineering and Technology
• /
• v.50 no.1
• /
• pp.203-210
• /
• 2018

As the modernization of the nuclear instrumentation system progresses, research reactors have adopted digital wide-range neutron power measurement (DWRNPM) systems. These systems typically monitor the neutron flux across a range of over 10 decades. Because neutron detectors only measure the local neutron flux at their position, the local neutron flux must be converted to total reactor power through calibration, which involves mapping the local neutron flux level to a reference reactor power. Conventionally, the neutron power range is divided into smaller subranges because the neutron detector signal characteristics and the reference reactor power estimation methods are different for each subrange. Therefore, many factors should be considered when preparing the calibration procedure for DWRNPM channels. The main purpose of this work is to serve as a reference for performing the calibration of DWRNPM systems in research reactors. This work provides a comprehensive overview of the calibration of DWRNPM channels by describing the configuration of the DWRNPM system and by summarizing the theories of operation and the reference power estimation methods with their associated calibration procedure. The calibration procedure was actually performed during the commissioning of an open-pool type research reactor, and the results and experience are documented herein.

• Journal of IKEEE
• /
• v.7 no.2 s.13
• /
• pp.245-252
• /
• 2003

We designed a silicon pressure sensor interface circuit with digital calibration capability. The interface circuit is composed of an analog section and a digital section. The analog section amplifies the weak signal from the sensor and the digital section handles the calibration function and communication function between the chip and outside microcontroller that controls the calibration. The digital section is composed of I2C serial interface, memory, trimming register and controller. The I2C serial interface is optimized to suit the need of on-chip silicon microsensor in terms of number of IO pins and silicon area. The major part of the design is to build a controller circuit that implements the optimized I2C protocol. The designed chip was fabricated through IDEC's MPW. We also made a test board and the test result showed that the chip performs the digital calibration function very well as expected.

• Ocean Systems Engineering
• /
• v.1 no.3
• /
• pp.195-205
• /
• 2011

A method for calibrating a laser profiling system for seafloor micro-topography measurements is described. The system consists of a digital camera and an arrangement of six red lasers that are mounted as a unit on a remotely operated vehicle (ROV). The lasers project as parallel planes onto the seafloor, creating profiles of the local topography that are interpreted from the digital camera image. The goal of the calibration was to determine the plane equations for the six lasers relative to the camera. This was accomplished in two stages. First, distortions in the digital image were corrected using an interpolation method based on a virtual pinhole camera model. Then, the laser planes were determined according to their intersections with a calibration target. The position and orientation of the target were obtained by a registration process. The selection of the target shape and size was found to be critical to a successful calibration at sea, due to the limitations in the manoeuvrability of the ROV.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.13 no.3
• /
• pp.35-42
• /
• 2017

This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.9 no.3
• /
• pp.59-65
• /
• 2013

This paper presents a novel calibration method for a base station system adopting an antenna array. The proposed technique utilizes Zadoff-Chu sequence, which is included in the LTE pilot signal periodically, in order to compute the phase characteristic of each antenna channel. As the Zadoff-Chu sequence exhibits an excellent autocorrelation characteristic, it is possible for the receiving base station to retrieve the Zadoff-Chu sequence transmitted from each mobile terminal. In addition, we can obtain the phase characteristic of each antenna channel, which is the ultimate goal of the calibration procedure. The proposed calibration algorithm has been implemented using an FPGA (Field Programmable Gate Array). We have applied the proposed algorithm to an array consisting of 2 antenna elements for simplicity. the phase value implied to the first and second antenna path is very accurately calculated from the proposed procedure. From the experimental test, the proposed method provides accurate calibration results.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.1
• /
• pp.1-9
• /
• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• Journal of Astronomy and Space Sciences
• /
• v.19 no.4
• /
• pp.293-304
• /
• 2002

This paper describes the re-design and the calibration results of the MAG digital circuit onboard the KSR-3. We enhanced the sampling rate of magnetometer data. Also, we reduced noise and increased authoritativeness of data. We could confirm that AIM resolution was decreased less than InT of analog calibration by a digital calibration of magnetometer. Therefore, we used numerical-program to correct this problem. As a result, we could calculate correction and error of data. These corrections will be applied to magnetometer data after the launch of KSR-3.