• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2000년도 전력전자학술대회 논문집
• /
• pp.163-167
• /
• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• Journal of electromagnetic engineering and science
• /
• 제17권3호
• /
• pp.138-146
• /
• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• ETRI Journal
• /
• 제29권4호
• /
• pp.463-469
• /
• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• 한국통신학회:학술대회논문집
• /
• 한국통신학회 1987년도 춘계학술발표회 논문집
• /
• pp.82-85
• /
• 1987

This paper describes the technology for the improvement of subxdriber loop utilization. Nearly all customer loops are now carried at voice frequency on individual wire pairs. Reenct digital technology improvements together with the increasing cost of wire, have resulted in some penetration of carrier systems into the loop plant. Moreover the increasing use of local digital switching systems should permit digital carrier systems to become an important factor in the loop plant in the future.

• 한국컴퓨터정보학회논문지
• /
• 제4권2호
• /
• pp.105-112
• /
• 1999

확산대역통신은 CDMA 시스템에서의 핵심기술이지만 SS통신에서의 문제점은 동기 방법이다. 동기방법에는 DLL(Delay Lock Loop), Tau-dither Loop, SO(Synchronous Osillator) 등이 있다. 그러나 아날로그 동작시에는 회로의 크기가 커지고 조정이 어려운 문제가 있어 본논문에서는 Digital Delay Lock Loop (DDLL)을 제안하고 실험을 통해 그 성능을 평가하였다.

• Journal of Power Electronics
• /
• 제11권2호
• /
• pp.113-119
• /
• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• 대한전기학회논문지:전력기술부문A
• /
• 제48권9호
• /
• pp.1131-1139
• /
• 1999

In this paper, we present a wide-bandwidth digital rebalance loop for a dynamically tuned gyroscope(DTG) based on {{{{ { H}_{2 } }}}} methodology. The operational principle and the importance of a rebalance loop are explaind, first. The augmented plant model is constructed, which includes a gyroscope model and an integrator. An {{{{ { H}_{ 2} }}}} based controller is designed for the augmented plant model. To verify the performance of the controller, a digital rebalance loop for a DTG is designed, fabricated and experimented. Through frequency response analyses and experiments using a real DTG, it is confirmed that the controller is more robustly stable and has a wider bandwidth compared with those of a conventional PID controller, contributing to the performance improvement of a DTG.

• 한국통신학회논문지
• /
• 제21권8호
• /
• pp.2043-2054
• /
• 1996

In this paper, Digital Delay Locked Loop(DDLL) is designed, implemented and analysed by experiment whose results show that it is possible to track the received signal by this scheme. Designed digital DLL has an advantage that it is not needed to maintain gain balance between early and late channels, which has been problem with an analog DLL. Also DDLL has more improved noise performance compared to analog DLL due to noise level limitation and noise cancellation characteristics. For various loop parameters, their effects on loop performance are analysed and simulated. Proposed DDLL is the first attempt as a digital approach in code tracking loop and it is expected to be a good reference for spread spectrum communication research.

• Journal of Power Electronics
• /
• 제10권5호
• /
• pp.518-527
• /
• 2010

This paper presents a new technique for directly designing a linear digital controller for a single-phase pulse width modulation (PWM) converter systems, based on closed-loop identification. The design procedure consists of three steps. First, obtain a digital current controller for the inner loop system by using the error space approach, so that the power factor of the supply is close to one. The outer loop is composed of a voltage controller, a current control loop including a current controller, a PWM converter, and a capacitor. Then, all the components, except the voltage controller, are identified by a discrete-time equivalent linear model, using the closed-loop output error (CLOE) method. Based on this equivalent model, a proper digital voltage controller is then directly designed. It is shown through PSim simulations and experimental results that the proposed method is useful for the practical design of PWM converter controllers.

• 한국광학회지
• /
• 제13권5호
• /
• pp.377-383
• /
• 2002

개회로 구성의 FOG용 All-Digital Closed Loop(ADCL) 신호처리기는 종래의 아날로그 방식의 위상추적 신호처리를 디지털로 구현한 것으로 안정화기를 채용하지 않고 이를 FOG에 적용하였을 때 0.26$\mu$rad/$^{\circ}C$의 온도의존성을 가지기 때문에 중급 이상의 FOG(fiber optics gyroscope)용 신호처리기로서는 문제가 있다. 온도드리프트는 위상변조를 위해 사용되는 위상변조기의 변조진폭과 위상지연의 온도드리프트에 의해 발생하는 것으로 FOG의 출력에서 위상변조신호의 고조파 성분의 비를 일정하게 함으로 써 광섬유 위상변조기의 동작을 안정화하여 FOG의 드리프트를 측정 불가한 수준으로 줄일 수 있었다.