• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Journal of Power Electronics
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• v.13 no.5
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• pp.757-765
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• 2013

For conventional interleaved two-phase forward converters with a common output inductor, the maximum duty cycle is 0.5, which limits the voltage range and increases the difficulty of the transformer's optimization. A new two-phase hybrid forward converter with series-parallel auto-regulated transformer windings is presented in this paper. With interleaved control signals for the two phases, the secondary windings of the transformers can work in series when the duty cycle is larger than 0.5, and they can work in parallel when duty cycle is lower than 0.5. Therefore, the maximum duty cycle is extended and the turns ratio of the transformer can be optimized. Duty cycle dependent auto-regulated windings result in the steady states of the converter being different in different duty cycle ranges (D>0.5 and D<0.5). Fortunately, the steady state gains of the proposed hybrid converter are identical at different duty cycle ranges, which means a stepless shift between two states. A prototype is built to verify the theoretical analysis. A conventional control loop is compatible for the whole input voltage range and load range thanks to the stepless shifting between the different duty cycle ranges.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.51-58
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• 2013

A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-${\mu}m$ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.55 no.10
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• pp.399-409
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• 2006

This paper presents a novel method for satisfying the thermal comfort of indoor environment and reducing the summer peak demand power by minimizing the power consumption for an Air-conditioner within a space. Korea Electric Power Corporation (KEPCO) use the fixed duty cycle control method regardless of the indoor thermal environment. However, this method has disadvantages that energy saving depends on the set-point value of the Air-Conditioner and direct load control (DLC) has no net effects on Air-conditioners if the appliance has a lower operating cycle than the fixed duty cycle. In this paper, the variable duty cycle control method is proposed in order to compensate the weakness of conventional fixed duty cycle control method and improve the satisfaction of residents and the reduction of peak demand. The proposed method estimates the predict mean vote (PMV) at the next step with predicted temperature and humidity using the back propagation neural network model. It is possible to reduce the energy consumption by maintaining the Air-conditioner's OFF state when the PMV lies in the thermal comfort range. To verify the effectiveness of the proposed variable duty cycle control method, the case study is performed using the historical data on Sep. 7th, 2001 acquired at a classroom in Seoul and the obtained results are compared with the fixed duty cycle control method.

• Journal of Power Electronics
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• v.7 no.2
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• pp.118-123
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• 2007

This paper presents a new ZCS-PWM high frequency inverter. Zero current switching operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. Dual duty cycle control scheme is used to provide a wide range of high frequency AC output power regulation that is important in many high frequency inverter applications. It found that a complete soft switching operation can be achieved even for low power setting ranges by introducing high-frequency dual duty cycle control scheme. The proposed high frequency inverter is more suitable for consumer induction heating(IH) applications. The operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

• The Journal of Korean Society for Radiation Therapy
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• v.27 no.1
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• pp.23-30
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• 2015

Purpose : External markers respiratory movement measuring device (RPM; Real-time Position Management, Varian Medical System, USA) Liver Cancer Radiation Therapy Respiratory gated with respiratory signal with irradiation time and the actual research by analyzing the respiratory phase with the breathing motion measurement device respiratory tuning evaluate the accuracy of radiation therapy Materials and Methods : May-September 2014 Novalis Tx. (Varian Medical System, USA) and liver cancer radiotherapy using respiratory gated RPM (Duty Cycle 20%, Gating window 40% ~ 60%) of 16 patients who underwent total when recording the analyzed respiratory movement. After the breathing motion of the external markers recorded on the RPM was reconstructed by breathing through the acts phase analysis, for Beam-on Time and Duty Cycle recorded by using the reconstructed phase breathing breathing with RPM gated the prediction accuracy of the radiation treatment analysis and analyzed the correlation between prediction accuracy and Duty Cycle in accordance with the reproducibility of the respiratory movement. Results : Treatment of 16 patients with respiratory cycle during the actual treatment plan was analyzed with an average difference -0.03 seconds (range -0.50 seconds to 0.09 seconds) could not be confirmed statistically significant difference between the two breathing (p = 0.472). The average respiratory period when treatment is 4.02 sec (${\pm}0.71sec$), the average value of the respiratory cycle of the treatment was characterized by a standard deviation 7.43% (range 2.57 to 19.20%). Duty Cycle is that the actual average 16.05% (range 13.78 to 17.41%), average 56.05 got through the acts of the show and then analyzed% (range 39.23 to 75.10%) is planned in respiratory research phase (40% to 60%) in was confirmed. The investigation on the correlation between the ratio Duty Cycle and planned respiratory phase and the standard deviation of the respiratory cycle was analyzed in each -0.156 (p = 0.282) and -0.385 (p = 0.070). Conclusion : This study is to analyze the acts after the breathing motion of the external markers recorded during the actual treatment was confirmed in a reproducible ratios of actual treatment of breathing motion during treatment, and Duty Cycle, planned respiratory gated window. Minimizing an error of the treatment plan using 4DCT and enhance the respiratory training and respiratory signal monitoring for effective treatment it is determined to be necessary.

• Proceedings of the KIEE Conference
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• 2005.11b
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• pp.145-147
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• 2005

This paper presents a methodology for satisfying the thermal comfort of Indoor environment and reducing the summer peak demand power by minimizing the power consumption for an Air-conditioner within a space. KEPCO(Korea Electric Power Corporation) use the fixed duty cycle control method regardless of the indoor thermal environment. This method has disadvantages that energy saying depends on the set-point value of the Air-Conditioner and DLC has no net effects on Air-conditioners if the appliance has a lower operating cycle than the fixed duty cycle. A variable duty cycle estimates the PMV(Predict Mean Vote) at the next step with a predicted temperature and humidity coming from the back propagation neural network model. It is possible to reduce the energy consumption by maintaining the Air-conditioner's OFF state when the PMV lies in the thermal comfort range. The proposed methodology uses the historical real data of Sep. 7th, 2001 from a classroom in seoul to verify the effectiveness of the variable duty cycle method comparing with fixed duty cycle. The result shows that the variable duty cycle reduces the peak demand to 2.6times more than fixed duty cycle and increases the load control ratio by 8% more. Based on the variable duty cycle control algorithm, the effectiveness of DLC is much more improved as compared with the fixed duty cycle.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.29-34
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• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.129-131
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• 2006

This paper presents a new ZVS-PWM high frequency inverter. The ZVS operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. The operating principle and the operating characteristics of the new high frequency circuit treated here are illustrated and evaluated on the basis of simulation results. It was examined that the complete soft switching operation can be achieved even for low power setting ranges by introducing the high frequency dual duty cycle control scheme. In the proposed high frequency inverter treated here, the dual mode pulse modulation control strategy of the asymmetrical PWM in the higher power setting ranges and the lower power setting ones, the output power of this high frequency inverter could introduce in order to extend soft switching operation ranges. Dual duty cycle is used to provide a wide range of output power regulation that is important in many high frequency inverter applications. It is more suitable for induction heating applications the operation and control principle of the proposed high frequency inverter are described and verified through simulated results.