• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1233-1238
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• 2010

The lighting industry has become the bigger and more systemized using the semiconductor LED with each control R(Red), G(Green), B(Blue). The communication standard DMX512(ANSI E1.11) protocol of it basically needs the address which can be distinguished between the lighting terminals. The conventional method has to give the address of the lighting any methods like dip switch, EEROM and PROM. Then the lighting terminal can receive RGB data from DMX512 communication. According to electrical characteristics DMX512 protocol has to the splitter every 32 lighting terminals. If 512 lightings is all connected, maximum 16 splitters are needed. This paper is solved above weakness in DMX512 protocol using serial connection all lighting terminals. Also I developed the intelligent lighting terminal with auto-addressing. This was solved the inconvenience of the address assignment and the usage of the splitter. The developed products is applied and selled the semiconductor lighting terminals using ON-OFF control, dimming control, sequential control and rainbow control.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.6
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• pp.251-257
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• 2014

An actuator system is a type of motor designed to control a mechanism operated by a source of energy, in the form of an electric current by converting energy into some kind of motion. As audio actuators, transforming electric voltage signal into audio signal, speakers and amplifiers are commonly used. In applications of industry, high output power systems are required. For these systems to generate high-quality output, it is essential to control output impedance of audio systems. We have developed an adaptable power supply for driving active amplifier systems with variable loads. Depending on the changing values of resistance of the speaker which produces audible sound by transforming electric voltage signal, the power supply source of the active amplifier can generate the maximum power delivered to the speaker by an adaptable change of loads. The amplifier is well protected from the abrupt increment of peak current and an excess of current flow.

• 대한공업교육학회지
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• v.33 no.2
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• pp.325-339
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• 2008

In this paper, we developed a module that can execute the data acquisition of the real-time measured radiant rays in the specific part of the nuclear power station. This module that includes the RF communication function, paces around the power station, being loaded on robot and can obtain the generated radiant rays in the various places through the detecting devices. It is considered that this new developed radiant rays acquisition method will have the higher degree of efficiency as compared with the existing method and reduce the expenses of the maintenance and repair work.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.30-37
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• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.5
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• pp.169-177
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• 2003

We establish the security requirements and derive a generic condition of elliptic curve scalar multiplication to resist against DPA and Goubin’s attack. Also we show that if a scalar multiplication algorithm satisfies our generic condition, then both attacks are infeasible. Showing that the randomized signed scalar multiplication using Ha-Moon's receding algorithm satisfies the generic condition, we recommend the randomized signed scalar multiplication using Ha-Moon's receding algorithm to be protective against both attacks. Also we newly design a random recoding method to Prevent two attacks. Finally, in efficiency comparison, it is shown that the recommended method is a bit faster than Izu-Takagi’s method which uses Montgomery-ladder without computing y-coordinate combined with randomized projective coordinates and base point blinding or isogeny method. Moreover. Izu-Takagi’s method uses additional storage, but it is not the case of ours.