• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.7
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• pp.601-604
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• 2006

In this paper, we propose the single poly-Si Flash EEPROM device with a new structure which does not need the high voltage switching circuits. The device was designed, fabricated and characterized. From the measurement results, it was found that the program, the erase and the read operations worked properly. The threshold voltage was 3.1 V after the program in which the control gate and the drain were biased with 12 V and 7 V for $100{\mu}S$, respectively. And it was 0.4 V after the erase in which the control gate was grounded and the drain were biased with 11 V for $200{\mu}S$. On the other hand, it was found that the program and the erase speeds were significantly dependent on the capacitive coupling ratio between the control gate and the floating gate. The larger the capacitive coupling ratio, the higher the speeds, but the target the area per cell. The optimum structure of the cell should be chosen with the consideration of the trade-offs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.455-461
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• 2017

In this paper, a local DL (Data Line) sensing method with smaller parasitic capacitance replacing the previous distributed DB sensing method with large parasitic capacitance is proposed to reduce the time to transfer BL (Bit Line) voltage to DL in the read mode. A new BL switching circuit turning on NMOS switches faster is also proposed. Furthermore, the access time is reduced to 35.63ns from 40ns in the read mode and thus meets the requirement since BL node voltage is clamped at 0.6V by a DL clamping circuit instead of precharging the node to VDD-VT and a differential amplifier are used. The layout size of the designed 512Kb EEPROM memory IP based on a $0.13{\mu}m$ BCD is $923.4{\mu}m{\times}1150.96{\mu}m$ ($=1.063mm^2$).

• Journal of Korea Multimedia Society
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• v.10 no.8
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• pp.1029-1038
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• 2007

A smart card based on the existing Java card platform executes and installs an application only when the power is supplied for a minute. And preparing for unexpected power outrage, the execution state of an application and all the data that are modified during execution are saved in the heap. This kind of frequent data update of an EEPROM data is a main cause of reducing the life-cycle of a smart card. This is because the smart card has been developed not considering the current situation that the power is always supplied, and by this time it has continuously kept its old architecture. This paper explains the high performance Java card system free power restriction. The system improves not only application saving mechanism, but memory architecture. In special, we deploy RAM for running an applet, as well as EEPROM for downloading an application. Through proposed mechanism, we can find out performance evaluation that the creation speed of an applet and the execution speed of a method increase up to 58% and 33% respectively.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.21-27
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• 1999

In this work, single-poly EEPROM was designed and fabricated by using standard $0.8{\mu}m$ CMOS process. From the results of programming and erasing characteristics, it was found that the programming time was smaller than 10ms and the erasing time was about 100ms. To reduce the erasing time, several erasing methods were performed. The S/D erasing method was used to improve the endurance characteristics which was degraded due to electron trapping in programming and erasing cycles. By using the S/D erasing method, the more improved endurance characteristics then conventional one was obtained.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.163-170
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• 1999

A programmable A/D converter for an embedded fiber-optic combustion pressure sensor has been designed with 8 N and P channel MOSFETs, respectively. A local field enhancement for reducing programming voltage during writing as well as erasing an EEPROM device is introduced. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a $1.2\;{\mu}m$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10mVolt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, $37\;{\mu}W$ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.48-51
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• 1991

Short channel Nonvolatile EEPROM memory devices were fabricated to CMOS 1M bit design rule, and reviews the characteristics and applications of SNOSFET. Application of SNOS field effect transistors have been proposed for both logic circuits and nonvolatile memory arrays, and operating characteristics with write and erase were investigated. As a results, memory window size of four terminal devices and two terminal devices was established low conductance stage and high conductance state, which was operated in “1” state and “0”state with write and erase respectively. And the operating characteristics of unit cell in matrix array were investigated with implementing the composition method of four and two terminal nonvolatile memory cells. It was shown that four terminal 2${\times}$2 matrix array was operated bipolar, and two termineal 2${\times}$2 matrix array was operated unipolar.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.425-428
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• 1998

In this work, single-poly EEPROM has been designed and fabricated by using standard 0.8.mu.m CMOS process. The initial threshold voltage was aobut 0.8V but it increased ot about 6.5V after programming at Vds=11.5V and Vcg=6.5V. After erasing devices at Vs=14.2V, the threshold voltage decreased to about 1.5V. The programming time and erasing trime wree about 6ms. and 100ms. respectively. The erasing time can be reduced by applying a series of shorter erase pulse s instead of a long single erase pulse.

• Electrical & Electronic Materials
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• v.6 no.1
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• pp.28-33
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• 1993

Short channel 비휘발성 SNOSFET EEPROM 기억소자를 CMOS 1 Mbit 설계규칙에 따라 제작하고 특성과 응용을 조사하였다. 논리 어레이를 실현하기 위한 SNOSFET는 4단자와 2단자 비휘발성 메모리 셀로 구성하고 이에 대한 기록과 소거 특성을 조사하였다. 결과적으로 4단자 소자와 2단자 소자의 메모리 윈도우는 각각 기록과 소거에 의하여 "1"상태와 "0"상태로 동작되는 저전도 상태와 거전도 상태를 나타냈다. 4단자 2 x 2 메트릭스 어레이는 양극성으로 동작하였으며 2단자 2 x 2 메트릭스 어레이는 단극성으로 동작하였다.릭스 어레이는 단극성으로 동작하였다.