• Electrical & Electronic Materials
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• v.7 no.2
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• pp.165-175
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• 1994

1967년 Wegener등과 Khang등이 각각 구조 및 동작원리가 다른 비휘발성 반도체 메모리(nonvolatile semiconductor memory)를 최초로 개발, 도입한 이후 3세대째를 보내고 있는 현재, 메모리는 반도체산업의 선봉으로써 여전히 공정기술(processing technology)을 이끌며, 시장점유율, 응용범위등에서 주도적 위치를 차지하고 있다. 한편, 최근의 컴퓨터 시스템은 소형화, 저전력화, 고속화, 내충격성 등 기술적 측면에서 뿐만 아니라 소프트웨어적으로도 급격히 발전하고 있다. 이에 따라 메모리부분에 있어서도 기존의 자기 하드디스크 메모리(magnetic hard disk memory)의 한계를 극복하기 위해서 반도체 메모리로서 대체가 더욱 요구되고 있다. 이와같은 상황에서 EEPROM(electrically erasable and programmable ROM)은 상주 시스템내에서도 전기적 방법에 의해 사용자가 임으로 기록/소거(write/erase)할 수 있을 뿐만 아니라 전원이 제거된 상테에서도 기억상태를 유지할 수 있는 비휘발성이라는 점에서 차세대 반도체 메모리 부문의 주역으로서 주목받고 있다. 따라서, 본 고에서는 20세기를 보내며 반도체메모리의 새로운 장을 열어가는 EEPROM의 기술현황 및 전망에 관해 살펴보고자 한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.05a
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• pp.127-129
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• 1994

For scale-down EEPROM, MONOS structures with the different thicknesses of gate insulators, are fabricated and the memory characteristics, such as swtching and retention characteristics are investigated. As a results, the devices with the top oxide of 20A thick were deteriorated in retentivity. However, 11V-programmable voltage for ΔV$\sub$FB/=4V and 10-year data retention were achieved in MONOS structure with the t7p oxide of 50 ${\AA}$ thick and nitride 45${\AA}$thick.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.584-587
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• 2003

UICC는 애플리케이션, 파일 시스템, 보안 메커니즘, 암호 알고리즘 등을 포함하고 있는 일종의 스마트 카드이다. UICC의 파일은 ISO7816-4 표준에서 정의한 파일들과 애플리케이션의 최상 위 파일인 Application Dedicated file등이 있다. UICC가 자바 카드 기반에서 구현되 었을 때 모든 파일은 객체로서 구체화될 수 있다. 이 때 각 파일 객체는 파일에 대한 정보들과 정보 조작과 관련된 메소드를 제공하게 된다. 자바 카드는 일반 컴퓨터와 유사하지만 제한적인 메모리와 처리속도 등으로 인하여 구현 상 많은 제약사항이 따른다. 자바카드는 저장 공간을 ROM, RAM, EEPROM로 구분할 수 있으며, 파일이나 애플릿, 데이터 등은 EEPROM 영역에 저장된다. 하지만 자바 카드가 지원하는 EEPROM영역이 2.2.1 버전에서 확장되었다 할지라도 여전히 많은 데이터를 저장하기에는 부족한 메모리 공간을 갖는다. 이것은 메모리 사용에 있어 신중을 기해야 한다는 것을 의미하며 효율적인 메모리 사용은 카드 사용자에게 보다 많은 가용 메모리를 제공할 수 있다는 점에서 중요하다. 본 논문에서 는 이러한 점을 고려하여 자바 카드에서 UICC의 파일 시스템을 Linked List 방식을 이용하여 구현하는 방법과 배열을 이용하여 구현하는 방법을 제시하고 파일 시스뎀의 전체적인 구조를 효율적으로 구성하는 방법을 제시한다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.9-16
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• 1999

When the conventional IPD (inter-poly-dielctrics) layer with ONO(oxide-nitride-oxide) structure was used in the Flash EEPROM cell, its data retention characteristics were significanfly degraded because the top oxide of the ONO layer was etched off due to the cleaning process used in the gate oxidation process for the peripheral MOSFETs. When the IPD layer with the ONON(oxide-nitride-oxide-nitride) was used there, however, its data retention characteristics were much improved because the top nitride of the ONON layer protected the top oxide from being etched in the cleaning process. For the modelling of the data retention characteristics of the Flash EEPROM cell with the ONON IPD layer, the decrease of the threshold voltage cue to the charge loss during the bake was here given by the empirical relation ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$ and the values of the ${\beta}$=184.7, m=0.224, Ea=0.31 eV were obtained with the experimental measurements. The activation energy of 0.31eV implies that the decrease of the threshold voltage by the back was dur to the movement of the trapped electrons inside the inter-oxide nitride layer. On the other hand, the results of the computer simulation using the model were found to be well consistent with the results of the electrical measurements when the thermal budget of the bake was not high. However, the latter was larger then the former in the case of the high thermal budger, This seems to be due to the leakage current generated by the extraction of the electrons with the bake which were injected into the inter-oxide niride later and were trapped there during the programming, and played the role to prevent the leakage current. To prevent the generation of the leakage current, it is required that the inter-oxide nitride layer and the top oxide layer be made as thin and as thick as possible, respectively.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.56-62
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• 1999

All the cells on the whole memory array or a block of the memory array in the Flash EEPROM's are erased at the same time using Fowler-Nordheim (FN) tunneling. some of the cels are often overerased since the tunneling is not a self-limited process. In this paper, the optimum doping concentration of the floating gate solve the overerase problem has been studied. For these studies, N-type MOSFETs and MOS capacitors with various doping concentrations of the gate polysilicon have been fabricated and their electrical characteristics have been measured and analyzed. As the results of the experiment, it has been found that the overerase problem can be prevented if the doping concentration of the floating gate is low enough (i.e. below $1.3{\times}10^{18}/cm^3$). It is because the potential difference between the floating gate and the source is lowered due to the formation of the depletion layer in the floating gate and thus the erasing operation stops by itself after most of the electrons stored in the floating gate are extracted. On the other hand, the uniformity of the Vt and the gm has been significantly poor if the coping concentration of the floating, gate is too much lowered (i.e. below $1.3{\times}10^{17}/cm^3$), which is believed to be due to nonuniform loss of the dopants from the nonuniform segregation in the floating gate. Consequently, the optimum doping concentration of the floating gate to suppress the overerase problem and get the uniform Vt and has been found to range from $1.3{\times}10^{17}/cm^3$ to $1.3{\times}10^{18}/cm^3$ in the Flash EEPROM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.55-55
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• 2001

개의 N과 P채널 EEPROM을 이용하여 A/D 변환기를 설계하였다. 프로그래밍 모드에서 EEPROM의 선형적 저장능력을 관찰하기 위해 MOSIS의 1.2㎛ double-poly CMOS 공정을 이용하여 셀이 제작되었다. 그 결과 1.25V와 2V구간에서 10㎷ 미만의 오차 내에서 셀이 선형적으로 프로그램 되는 것을 보았다. 이러한 실험 결과를 이용하여 프로그램 가능한 A/D 변환기의 동작이 Hspice에서 시뮤레이션 되었으며, 그 결과 A/D 변환기가 37㎼의 전력을 소모하고 동작주파수는 333㎒ 정도인 것으로 관찰되었다.

• Proceedings of the Korea Multimedia Society Conference
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• 2004.05a
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• pp.354-357
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• 2004

자바는 스마트 카드 상의 다중 애플리케이션 기능을 지원하기 위한 가장 유용한 프로그래밍 언어이다. $\lrcorner$CVM(Java Card Virtual Machine)은 자바 언어로 작성된 프로그램들을 스마트 카드 상에서 동작 가능하게 한다. 현재 스마트 카드는 작은 프로세서를 가지고 있으며 이런 제한적인 환경에서의 JCVM 성능 향상은 매우 중요한 이슈 중의 하나이다 그리고 기존의 스마트 카드는 쓰기 속도가 느린 EEPROM에 객체를 생성하여 사용함으로 JCVM의 성능 저하를 가져왔다. 본 논문에서는 스마트 카드 메모리 관리, 즉, EEPROM에서 RAM으로 객체를 이동시킴으로써 JCVM 성능을 보다 향상시키는 알고리즘에 관해 제안하고자 한다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.375-378
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• 2013

A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's $0.18{\mu}m$ EEPROM process uses a low-voltage bandgap reference voltage generator of cascode current-mirror type with a wide swing and shows a reference voltage characteristic insensitive to PVT variation. The minimum operating voltage is 1.43V and the VREF sensitivity against VDD variation is 0.064mV/V. Also, the VREF sensitivity against temperature variation is $20.5ppm/^{\circ}C$. The VREF voltage has a mean of 1.181V and its three sigma ($3{\sigma}$) value is 71.7mV.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.277-288
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• 2002

In this paper, we describe a design and implementation method of a smart card operating system for multi applications. A smart card is the independent computing system and is able to be used in multi applications such as the electronic commerce and the electronic cash. Smart card operation system(SCOS) provides a basis of smart card booting, and controls and manages application programs. SCOS can produce and control a file system to support multi applications in EEPROM, communicate commands and messages with outside devices, process a command, produce a reply message, and provide security functions of file security in EEPROM, and communication security. Therefor, in this paper, we design and implement SCOS system that provides the authentication between a card and a terminal, the session authentication for multi applications, the processing of commands, and the maintenance of the security.