• Korean Journal of Materials Research
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• v.6 no.6
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• pp.605-609
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• 1996

MOS 소자의 얇은산화막(thin oxide)불량을 화학적으로 식각하지 않고 불량부위를 광전자방사(photon emission)반응을 이용하여 위치를 확인하고, 이곳을 FIB로 절단하여 불량부위의 단면을 관찰했다. 20nm 두께의 SiO2불량은 셀(cell)영역의 위치에 따른 의존성은 없고, 불량은 저전계의 입자(particle)성 불량과 중간전계의 Si 기판 핏(pit)과 관련된 불량이 주였다. 고전계에서는 전형적인 SiO2 산화막의 절연파괴가 일어난 것이 관찰된다.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.30-36
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• 2020

We demonstrated a successful fabrication of 4" Gallium Nitride (GaN)/Diamond High Electron Mobility Transistors (HEMTs) incorporated with Inner Slot Via Hole process. We made in manufacturing technology of 4" GaN/Diamond HEMT wafers in a compound semiconductor foundry since reported [1]. Wafer thickness uniformity and wafer flatness of starting GaN/Diamond wafers have improved greatly, which contributed to improved processing yield. By optimizing Laser drilling techniques, we successfully demonstrated a through-substrate-via process, which is last hurdle in GaN/Diamond manufacturing technology. To fully exploit Diamond's superior thermal property for GaN HEMT devices, we include Aluminum Nitride (AlN) barrier in epitaxial layer structure, in addition to conventional Aluminum Gallium Nitride (AlGaN) barrier layer. The current collapse revealed very stable up to Vds = 90 V. The trapping behaviors were measured Emission Microscope (EMMI). The traps are located in interface between Silicon Nitride (SiN) passivation layer and GaN cap layer.