• Journal of Electrical Engineering and Technology
• /
• 제13권5호
• /
• pp.2033-2044
• /
• 2018

This study presents states-of-the art overview of the system level electrostatic discharge (ESD) analysis and testing. After brief description of ESD compliance standards and ESD coupling mechanisms, the study provides an in-depth review and comparison of the various techniques for the system level ESD coupling analysis using time and frequency domain techniques, full wave electromagnetic modeling and hybrid modeling. The methods used for improving system level ESD testing using troubleshooting and determining the root causes of soft failures, the optimization of ESD testing and the countermeasures to mitigate ESD problems are also discussed.

• 전기전자학회논문지
• /
• 제25권2호
• /
• pp.376-380
• /
• 2021

본 논문에서는 일반적인 SCR의 구조를 개선하여 높은 홀딩 전압으로 인한 래치 업면역 특성을 가지는 새로운 ESD 보호회로를 제안한다. 제안된 ESD회로의 특성검증을 위하여 Synopsys사의 TCAD를 이용하여 시뮬레이션을 진행하였으며, 기존 ESD 보호회로와 비교하여 제시하였다. 또한 설계변수 D1을 이용하여 전기적 특성의 변화를 검증하였다. 시뮬레이션 수행 결과 제안된 ESD 보호회로는 기존의 ESD 보호회로에 비해 높은 홀딩 전압특성과 양방향 방전특성을 확인하였다. 또한, Samsung의 0.13um BCD 공정을 이용하여 설계 후 TLP 측정을 통해 전기적 특성을 검증하였다. 이러한 과정을 통해 본 논문에서 제안된 ESD 보호회로 설계변수의 최적화를 진행하였고 향상된 홀딩 전압으로 래치 업 면역을 갖는다는 점에서 고전압 어플리케이션에 적용하기에 매우 적합함을 검증하였다.

• 조명전기설비학회논문지
• /
• 제16권4호
• /
• pp.108-116
• /
• 2002

본 논문은 인체에 대전된 정전기 방전전압 파형의 측정과 특성 분석에 관한 것으로 정전기 고속과도전압 측정기의 동작원리와 설계기법에 대하에 기술하였다. 여러 가지 실험조건에서 인체에 대전된 전하에 의해 발생한 정전기방전전압의 피크값과 상승시간을 분석하였다. 제안된 전압측정계의 주파수대역은 DC-400[MHz]이다. 각 실험조건에서 정전기 방전전압과 전류의 파형은 거의 비슷하였으며, 크기도 비례적 관계를 나타내었다. 빠른 접근일 때가 느린 접근일 때 보다 빠른 초기상승시간의 정전기방전전압이 나타났다. 인체에 의한 직접 방전전압은 비교적 초기상승시간이 10-30[ns]로 길었으나, 크기는 작았다. 반면에 손에 쥔 금속체를 통한 방전전압은 1~3[ns]의 짧은 상승시간을 가지며 피크값은 매우 크게 나타났다. 결국 정전기 방전전압과 전류 파형은 정전기 방전을 일으키는 접촉물체와 접근속도에 깊은 관계가 있음을 알았으며, 본 연구의 결과는 정전기 장해방지장치의 설계를 위한 기초자료로 활용될 것이다.

• ETRI Journal
• /
• 제38권2호
• /
• pp.272-279
• /
• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• 대한디지털의료영상학회논문지
• /
• 제15권2호
• /
• pp.13-18
• /
• 2013

Purpose : Fluoroscopy equipment, depending on the type of changes that occur in the patient's position ESD and study the patient's scatter ray of ESD Practitioners considered a comparative analysis was to evaluate the correct dose. Materials and Methods : HITACHI four overtube type TU-8000 Flat Detector and Under tube C-Arm Philips' Multi Diagnost Eleva with Flat Detector type were measured by. Each devices is a measure of the patient's esd randophantom position in tabel unfors Xi multi funtion then fixed to the abdomen fluoroscopy and 10 seconds, spot was measured three times, practitioners of the incident surface dose by considering the patient's scatter ray of the table for each device in the average human stomach 21cm thickness acrylic phantom ($25cm{\times}25cm$) Place the practitioner position after position randophantom unfors Xi multi funtion in the thyroid and stomach 1 minute by a fixed one-time fluoroscopy and measured. Results : 10 seconds and the patient perspective of the c-arm ESD 1.2 times smaller on the AP and oblique measurements were measured in the 6-13 times smaller. spot positions to changes in the measured three times on the AP of the abdomen, ESD is 18 times smaller c-arm measurements and the oblique measurement was 19-30 times smaller. And 1 minute at practitioners fluoroscopy esd in the thyroid 2.12 times the c-arm, chest 1.75 times less the dose was measured. On the AP, depending on the device, but the lack of dose difference oblique positions of the two devices depending on changes in the area due to changes in both the AP than on the dose increased, the difference in dose between the two devices, the maximum difference was approximately 27 times. Conclusion : Fluoroscopic equipment at the time of inspection in accordance with changes in dose according to the patient and the patient's positions changes, because the area of the scatter ray considering the change of dose measurements be made, and study of the equipment according to the characteristics of the efficiency and the exposure of the patient and practitioner is considered smooth study equipment manufacturers that can be done is to build the system and think that is also important. Various fluoroscopy when you check future changes in many factors of change in dose for the equipment in the laboratory system by considering the scatter ray radiation shielding for the management to take advantage of reckless undertube have been utilized as more exposure Reduction activities can help is considered as the direction.

• 대한전자공학회논문지SD
• /
• 제48권12호
• /
• pp.31-36
• /
• 2011

본 논문은 0.13um CMOS 공정에서 적층출력드라이버 ESD 내성에 대하여 조사 하였다. 실제적인 I/O 시스템과 유사하게 프리-드라이버와 파워 클램프를 포함한 적층출력드라이버 회로를 구현하였다. 프리-드라이버 입력 연결 방법과 적층출력드라이버의 NMOS 크기에 따라 8가지 회로를 구성하였으며, TLP 실험을 통해서 HBM 내성을 조사하였다. 그 결과 프리-드라이버의 입력에 전원전압을 인가하고 적층출력드라이버는 가급적 유사한 크기로 진행한 조건이 다른 조건들 보다 높은 항복전류와 항복전압을 보여주었다. 이 테스트 결과를 토대로, 적층출력드라이버의 ESD 내성을 향상시킬 수 있는 설계 가이드를 제안하였다.

• Asian Pacific Journal of Cancer Prevention
• /
• 제15권4호
• /
• pp.1803-1806
• /
• 2014

Endoscopic submucosal dissection (ESD) was originally developed for en bloc resection of large, flat gastrointestinal lesions. Compared with endoscopic mucosal resection (EMR), ESD is considered to be more time consuming and have more complications for treatment of early esophageal carcinoma, such as bleeding, stenosis and perforation. The objective of this study was to compare the efficacy and safety of ESD and EMR for such lesions. We searched databases, such as PubMed, EMBASE, Cochrane Library and Science Citation Index updated to 2013 for related trials. In the meta-analysis, the main outcome measurements were the en bloc resection rate, the histologically resection rate and the local recurrence rate. We also compared the operation time and the incidences of procedure-related complications. Five trials were identified, and a total of 710 patients and 795 lesions were included. The en bloc and histologically complete resection rates were higher in the ESD group compared with the EMR group (odds ratio (OR) 27.3; 95% CI, 11.5-64.8; OR 18.4; 95% CI, 8.82-38.59). The local recurrence rate was lower in the ESD group (OR 0.13, 95 % CI 0.04-0.43). The meta-analysis also showed ESD was more time consuming, but did not increase the complication rate (P=0.76). The results implied that compared with EMR, ESD showed better en bloc and histologically resection rates, and lower local recurrence, without increasing the incidence of procedure-related complications in the treatment of early esophageal carcinoma.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권3호
• /
• pp.401-410
• /
• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제8권3호
• /
• pp.227-231
• /
• 2008

A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a $0.35{\mu}m$ 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.

• ETRI Journal
• /
• 제39권5호
• /
• pp.746-755
• /
• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.