• Title/Summary/Keyword: Electronic packaging

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Thick Film Resistance Paste for Improving Reliability and TCR Properties of Embedded Resistor Board (내장형 저항 기판의 신뢰성과 TCR 개선을 위한 후막 저항 페이스트에 관한 연구)

  • Lee, S.M.;Yoo, M.J.;Park, S.D.;Kang, N.K.;Nam, S.
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.1
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    • pp.27-31
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    • 2008
  • Due to the increasing need for miniaturization of electronic device, embedded resistor technology using thick film resistance paste to embed resistors currently mounted on the board thus effectively reducing board size, is being extensively researched. In this research, thick film resistor paste having $0.35{\sim}4k{\Omega}/sq$ range of resistivity were fabricated using mixtures of carbon black and epoxy resin. In order to adjust the TCR (temperature coefficient resistivity), TCR modifiers such as Ni-Cr alloy, $SiO_2$ powder were added and were able to improve on TCR value with $100ppm/^{\circ}C$. Finally embedded resistor board using thick film resistance paste were fabricated. Stable resistivity value and reliability results were achieved.

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Transient Characteristic of a Metal-Oxide Semiconductor Field Effect Transistor in an Automotive Regulator in High Temperature Surroundings

  • Kang, Chae-Dong;Shin, Kye-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.4
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    • pp.178-181
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    • 2010
  • An automotive IC voltage regulator which consists of one-chip based on a metal-oxide semiconductor field effect transistor (MOSFET) is investigated experimentally with three types of packaging. The closed type is filled with thermal silicone gel and covered with a plastic lid on the MOSFET. The half-closed type is covered with a plastic case but without thermal silicone gel on the MOSFET. Opened type is no lid without thermal silicone gel. In order to simulate the high temperature condition in engine bay, the operating circuit of the MOSFET is constructed and the surrounding temperature is maintained at $100^{\circ}C$. In the overshoot the maximum was mainly found at the half-closed packaging and the magnitude is dependent on the packaging type and the surrounding temperature. Also the impressed current decreased exponentially during the MOSFET operation.

Nanocomposites for microelectronic packaging

  • Lee, Sang-Hyeon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.99.1-99.1
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    • 2016
  • The materials for an electronic packaging provide diverse important functions including electrical contact to transfer signals from devices, isolation to protect from the environment and a path for heat conduction away from the devices. The packaging materials composed of metals, ceramics, polymers or combinations are crucial to the device operating properly and reliably. The demand of effective charge and heat transfer continuous to be challenge for the high-speed and high-power devices. Nanomaterials including graphene, carbon nanotube and boron nitride, have been designed for the purpose of exploiting the high thermal, electrical and mechanical properties by combining in the matrix of metal or polymer. In addition, considering the inherent electrical and surface properties of graphene, it is expected that graphene would be a good candidate for the surface layer of a template in the electroforming process. In this talk, I will present recent our on-going works in nanomaterials for microelectronic packaging: 1) porous graphene/Cu for heat dissipations, 2) carbon-metal composites for interconnects and 3) nanomaterials-epoxy composites as a thermal interface materials for electronic packaging.

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Product and Properties of Embedded Capacitor by Aerosol Deposition (Aerosol Deposition에 의한 Embedded Capacitor의 제조 및 특성 평가)

  • Yoo, Hyo-Sun;Cho, Hyun-Min;Park, Se-Hoon;Lee, Kyu-Bok;Kim, Hyeong-Joon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.313-313
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    • 2008
  • Aerosol Deposition(AD) method is based on the impact consolidation phenomenon of ceramic fine particles at room temperature. AD is promising technology for the room temperature deposition of the dielectrics thin films with high quality. Embedding of passive components such as capacitors into printed circuit board is becoming an important strategy for electronics miniaturization and device reliability, manufacturing cost reduction. So, passive integration using aerosol deposition. In this study, we examine the effects of the characteristics of raw powder on the thickness, roughness, electrical properties of $BaTiO_3$ thin films. Thin films were deposited on the copper foil and copper plate. Electrical and material properties was investigated as a change of annealing temperature. We final aim the effects of before and after of laminated on the electrical properties and suit of embedded capacitor.

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Microjoining Process for MEMS and Electronic Packaging (MEMS와 전자 패키징을 위한 마이크로 접합 공정)

  • 유중돈
    • Journal of Welding and Joining
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    • v.22 no.4
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    • pp.24-28
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    • 2004
  • 마이크로 접합 공정은 미세 부품이나 박판의 접합에 사용되며, 이를 위해 다양한 공정이 개발되었다. 최근 MEMS(Micro Electro Mechanical System)활용 범위가 증가하고 있으며, MEMS에 사용되는 미세한 구조물의 접합이나 패키징에 접합 공정이 활용되고 있다. MEMS는 발전 단계이지만 전자 패키징(electronic packaging)은 성숙 단계인 반도체 산업에 사용되고 있다.(중략)

Insertion Loss Analysis According to the Structural Variant of Interposer (인터포저의 디자인 변화에 따른 삽입손실 해석)

  • Park, Jung-Rae;Jung, Cheong-Ha;Kim, Gu-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.28 no.4
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    • pp.97-101
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    • 2021
  • In this study, Insertion loss according to the structural variant of interposer to Through Silicon Via (TSV) and Redistributed Layer (RDL) was studied through design of experiment. 3-Factors was considered as a variant, TSV depth, TSV diameter, RDL width with factor arrangement method and the response surface method from 400 MHz to 20 GHz. As a result, it was confirmed that as the frequency increased, the effect of RDL width was decreased and the effect of TSV depth and TSV diameter was increased. Also within the analysis range, to increasing RDL width, decreasing TSV depth, and fixing TSV diameter about 10.7 ㎛ was observed optimal result of Insertion loss.

System-Driven Approaches to 3D Integration

  • Beyne Eric
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2005.09a
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    • pp.23-34
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    • 2005
  • Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

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