• Title/Summary/Keyword: Embedded Clock

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An Implementation of Clock Synchronization in FPGA Based Distributed Embedded Systems Using CDR (CDR을 사용한 FPGA 기반 분산 임베디드 시스템의 클록 동기화 구현)

  • Song, Jae-Min;Jung, Yong-Bae;Park, Young-Seak
    • IEMEK Journal of Embedded Systems and Applications
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    • v.12 no.4
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    • pp.239-246
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    • 2017
  • Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

A Cost-effective 60Hz FHD LCD Using 800Mbps AiPi Technology

  • Nam, Hyoung-Sik;Oh, Kwan-Young;Kim, Seon-Ki;Kim, Nam-Deog;Kim, Sang-Soo
    • Journal of Information Display
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    • v.10 no.1
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    • pp.37-44
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    • 2009
  • AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, thereby having the smallest possible number of interface lines between a timing controller and column drivers. A point-to-point architecture boosts the data rate and reduces the number of interface lines, because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi-level signalling, which results in a simple clock/data recovery circuitry. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per data pair is more than 800 Mbps.

Fault-tolerant clock synchronization for low-cost networked embedded systems (저비용 네트워크 기반 임베디드 시스템을 위한 시간동기 기술)

  • Lee, Dong-Ik
    • Journal of Sensor Science and Technology
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    • v.16 no.1
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    • pp.52-61
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    • 2007
  • Networked embedded systems using the smart device and fieldbus technologies are now found in many industrial fields including process automation and automobiles. However the discrepancy between a node's view of current time and the rest of the system can cause many difficulties in the design and implementation of a networked system. To provide a networked system with a global reference time, the problem of clock synchronization has been intensively studied over the decades. However, many of the existing solutions, which are mainly developed for large scale distributed computer systems, cannot be directly applied to embedded systems. This paper presents a fault-tolerant clock synchronization technique that can be used for a low-cost embedded system using a CAN bus. The effectiveness of the proposed method is demonstrated with a set of microcontrollers and DC motor-based actuators.

Implementing IEEE1588 based Clock Synchronization for Networked Embedded System (네트워크 기반 임베디드 시스템을 위한 IEEE1588 시간동기 구현)

  • Jeon, Jong-Mok;Kim, Dong-Gil;Kim, Eun-Ro;Lee, Dong-Ik
    • IEMEK Journal of Embedded Systems and Applications
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    • v.9 no.1
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    • pp.33-41
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    • 2014
  • This paper presents a IEEE1588 based clock synchronization technique for a sRIO (Serial RapidIO) network which is applied to a submarine system. Clock synchronization plays a key role in the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipset has been widely used for the synchronization of various industrial applications. However, there is no chipset available for the sRIO network that can offer many advantages, such as low latency and jitter. In this paper, the IEEE1588 algorithm for a sRIO network is implemented using only software without any dedicated chipset. The proposed approach is verified with experimental setup.

Clock Synchronization in Wireless Embedded Applications (무선 임베디드 환경에서의 시간 동기화)

  • No, Jin-Hong;Hong, Young-Sik
    • Journal of KIISE:Information Networking
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    • v.32 no.6
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    • pp.668-675
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    • 2005
  • With the proliferation of wireless network and the advances of the embedded systems, the traditional distributed systems begin to include the wireless embedded systems. Clock synchronization in the distributed systems is one of the major issues that should be considered for diverse Purposes including synchronization, ordering, and consistency. Many clock synchronization algorithms have been proposed over the years. Since clock synchronization in wireless embedded systems should consider the low bandwidth of a network and the poor resources of a system, most traditional algorithms cannot be applied directly. We propose a clock synchronization algorithm in wireless embedded systems, extending IEEE 802.11 standard. The proposed algorithm can not only achieve high precision by loosening constraints and utilizing the characteristics of wireless broadcast but also provide continuous time synchronization by tolerating the message losses. In master/slave structure the master broadcasts the time information and the stave computes the clock skew and the drift to estimate the synchronized time of the master. The experiment results show that the achieved standard deviation by the Proposed scheme is within the bound of about 200 microseconds.

A Clock Frequency Detector for Improving Certainty of the Embedded System (임베디드 시스템의 정확성 향상을 위한 클럭 주파수 검출기)

  • Jeong, Gwanghyeon
    • Journal of the Korea Institute of Military Science and Technology
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    • v.23 no.5
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    • pp.516-522
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    • 2020
  • In this paper, the frequency detector which detects the clock frequency of the embedded system is proposed and analyzed. The proposed frequency detector is consisted of filter and peak voltage detector. The clock signal is converted from square wave to triangular wave by the filter. The peak voltage of the triangular wave is determined according to the frequency response of filter. The peak voltage detector detects and holds the peak voltage of the signal. Moreover, the proposed clock frequency detector can detect the frequency within 1ms and it gives guarantee of real-time operation.

Design Methodologies for Reliable Clock Networks

  • Joo, Deokjin;Kang, Minseok;Kim, Taewhan
    • Journal of Computing Science and Engineering
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    • v.6 no.4
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    • pp.257-266
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    • 2012
  • This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

A Frequency Selection Algorithm for Power Consumption Minimization of Processor in Mobile System (이동형 시스템에서 프로세서의 전력 소모 최소화를 위한 주파수 선택 알고리즘)

  • Kim, Jae Jin;Kang, Jin Gu;Hur, Hwa Ra;Yun, Choong Mo
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.4 no.1
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    • pp.9-16
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    • 2008
  • This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

Leader-Following Sampled-Data Control of Wheeled Mobile Robots using Clock Dependent Lyapunov Function (시간 종속적인 리아프노프 함수를 이용한 모바일 로봇의 선도-추종 샘플 데이터 제어)

  • Ye, Donghee;Han, Seungyong;Lee, Sangmoon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.16 no.4
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    • pp.119-127
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    • 2021
  • The aim of this paper is to propose a less conservative stabilization condition for leader-following sampled-data control of wheeled mobile robot (WMR) systems by using a clock-dependent Lyapunov function (CDLF) with looped functionals. In the leader-following WMR system, the state and input of the leader robot are measured by digital devices mounted on the following robot, and they are utilized to construct the sampled-data controller of the following robot. To design the sampled-data controller, a stabilization condition is derived by using the CDLF with looped functionals, and formulated in terms of sum of squares (SOS). The considered Lyapunov function is a polynomial form with respect to the clock related to the transmitted sampling instants. As the degree of the Lyapunov function increases, the stabilization condition becomes less conservative. This ensures that the designed controller is able to stabilize the system with a larger maximum sampling interval. The simulation results are provided to demonstrate the effectiveness of the proposed method.

Cost Effective 60Hz FHD LCD with 800Mbps AiPi Technology

  • Nam, Hyoung-Sik;Oh, Kwan-Young;Kim, Seon-Ki;Kim, Nam-Deog;Berkeley, Brian H.;Kim, Sang-Soo;Lee, Yong-Jae;Nakajima, Keiichi
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.677-680
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    • 2008
  • AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, achieving the smallest possible number of interface lines between a timing controller and source drivers. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per one data pair is more than 800Mbps.

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