• Title/Summary/Keyword: Embedded Clock

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An Imbedded System for Time Synchronization in Distributed Environment based on the Internet (인터넷 기반 분산 환경에서 시각 동기를 위한 임베디드 시스템)

  • Hwang So-Young;Yu Dong-Hui;Li Ki-Joune
    • Journal of KIISE:Computing Practices and Letters
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    • v.11 no.3
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    • pp.216-223
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    • 2005
  • A computer clock has limits in accuracy and precision affected by its inherent instability, the environment elements, the modification of users, and errors of the system. So the computer clock needs to be synchronized with a standard clock if the computer system requires the precise time processing. The purpose of synchronizing clocks is to provide a global time base throughout a distributed system. Once this time base exists, transactions among members of distributed system can be controlled based on time. This paper discusses the integrated approach to clock synchronization. An embedded system is considered for time synchronization based on the GPS(Global Positioning System) referenced time distribution model. The system uses GPS as standard reference time source and offers UTC(Universal Time Coordinated) through NTP(Network Time Protocol). A clock model is designed and adapted to keep stable time and to provide accurate standard time with precise resolution. Private MIB(Management Information Base) is defined for network management. Implementation results and performance analysis are also presented.

The end effector of circadian heart rate variation: the sinoatrial node pacemaker cell

  • Yaniv, Yael;Lakatta, Edward G.
    • BMB Reports
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    • v.48 no.12
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    • pp.677-684
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    • 2015
  • Cardiovascular function is regulated by the rhythmicity of circadian, infradian and ultradian clocks. Specific time scales of different cell types drive their functions: circadian gene regulation at hours scale, activation-inactivation cycles of ion channels at millisecond scales, the heart's beating rate at hundreds of millisecond scales, and low frequency autonomic signaling at cycles of tens of seconds. Heart rate and rhythm are modulated by a hierarchical clock system: autonomic signaling from the brain releases neurotransmitters from the vagus and sympathetic nerves to the heart's pacemaker cells and activate receptors on the cell. These receptors activating ultradian clock functions embedded within pacemaker cells include sarcoplasmic reticulum rhythmic spontaneous Ca2+ cycling, rhythmic ion channel current activation and inactivation, and rhythmic oscillatory mitochondria ATP production. Here we summarize the evidence that intrinsic pacemaker cell mechanisms are the end effector of the hierarchical brain-heart circadian clock system.

Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

  • Jung, Hong-Kyun;Jin, Xianzhe;Ryoo, Kwang-Ki
    • Journal of information and communication convergence engineering
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    • v.10 no.1
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    • pp.78-84
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    • 2012
  • This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

Bandwidth Tracing Arbitration Algorithm for Mixed-Clock Systems with Dynamic Priority Adaptation

  • Kwon, Young-Su;Kyung, Chong-Min
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.959-962
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    • 2003
  • At the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms

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Active Page Replacement Policy for DRAM & PCM Hybrid Memory System (DRAM&PCM 하이브리드 메모리 시스템을 위한 능동적 페이지 교체 정책)

  • Jung, Bo-Sung;Lee, Jung-Hoon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.13 no.5
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    • pp.261-268
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    • 2018
  • Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

A Clock Synchronization protocol for Distributed Embedded Systems in wireless environments (무선환경에서 분산 임베디드 시스템을 위한 시간 동기화 기법)

  • 이윤준;홍영식
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.10c
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    • pp.220-222
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    • 2003
  • 최근 무선 임베디드 시스템의 사용이 증가하면서 기존의 분산 환경에 무선 임베디드 시스템이 포함되기 시작하였고, 이를 고려한 분산 어플리케이션들이 개발되고 있다. Global clock과 동기화할 수 있는 GPS가 모든 무선 임베디드 시스템에 장착되지 않은 상황에서 분산된 임베디드 시스템간 혹은 고성능 컴퓨터와의 내부 동기화를 수행할 동기화 기법이 필요하다. 현재 무선환경에서의 동기화에 대한 연구들이 이루어지고 있지만 제한된 리소스의 임베디드 시스템에 그대로 적용하기 어렵다. 이에 본 논문에서는 무선 임베디드 시스템만이 가지는 제한사항을 고려하여 메시지 지연값의 변화량을 측정하여 적용할 수 있는 시간 동기화 기법을 제시하고 실험을 통해 그 성능을 평가한다.

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A Dynamic Frequency Controlling Technique for Power Management in Existing Commercial Microcontrollers

  • Lueangvilai, Attakorn;Robertson, Christina;Martinez, Christopher J.
    • Journal of Computing Science and Engineering
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    • v.6 no.2
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    • pp.79-88
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    • 2012
  • Power continues to be a driving force in central processing units (CPU) design. Most of the advanced breakthroughs in power have been in a realm that is applicable to workstation CPUs. Advanced power management systems will manage temperature, dynamic voltage scaling and dynamic frequency scaling in a CPU. The use of power management systems for microcontrollers and embedded CPUs has been modest, and mostly focuses on very large scale integration (VLSI) level optimizations compared to system level optimizations. In this paper, a dynamic frequency controlling (DFC) technique is introduced, to lay the foundation of a system level power management system for commercial microcontrollers. The DFC technique allows a commercial microcontroller to have minor modifications on both the hardware and software side, to allow the clock frequency to change to save power; results in this study show a 10% savings. By adding an additional layer of software abstraction at the interrupt level, the microcontroller can operate without having knowledge of the current clock frequency, and this can be accomplished without having to use an embedded operating system.

A Study on Efficient Test Data Compression Method for Test-per-clock Scan (Test-per-clock 스캔 방식을 위한 효율적인 테스트 데이터 압축 기법에 관한 연구)

  • Park, Jae-Heung;Yang, Sun-Woong;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.9
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    • pp.45-54
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    • 2002
  • This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.

A 0.9-V human body communication receiver using a dummy electrode and clock phase inversion scheme

  • Oh, Kwang-Il;Kim, Sung-Eun;Kang, Taewook;Kim, Hyuk;Lim, In-Gi;Park, Mi-Jeong;Lee, Jae-Jin;Park, Hyung-Il
    • ETRI Journal
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    • v.44 no.5
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    • pp.859-874
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    • 2022
  • This paper presents a low-power and lightweight human body communication (HBC) receiver with an embedded dummy electrode for improved signal acquisition. The clock data recovery (CDR) circuit in the receiver operates with a low supply voltage and utilizes a clock phase inversion scheme. The receiver is equipped with a main electrode and dummy electrode that strengthen the capacitive-coupled signal at the receiver frontend. The receiver CDR circuit exploits a clock inversion scheme to allow 0.9-V operation while achieving a shorter lock time than at 3.3-V operation. In experiments, a receiver chip fabricated using 130-nm complementary metal-oxide-semiconductor technology was demonstrated to successfully receive the transmitted signal when the transmitter and receiver are placed separately on each hand of the user while consuming only 4.98 mW at a 0.9-V supply voltage.

Clock Pulse Synchronization of MCU Timers in Embedded Systems (임베디드 시스템 MCU 타이머 클록 펄스 동기화)

  • Lee, Hyung-Bong;Kwon, Ki-Hyeon
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.7
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    • pp.47-55
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    • 2013
  • Most of the applications implemented in embedded systems use timers equipped in MCU. The purposes of timer usage of the applications lie in a wide range of areas such as implementing software timers of real-time operating systems to measuring processing time of sensors. The elapsed times measured by the applications are various in length as well as in precision ranging from several us to several hundreds of ms. The paper analyzes the timing error factors caused by un- synchronizing timer clock pulse when timers are manipulated, and proposes a method of how to synchronize timer clock pulse to reduce the timing errors. As a result of an experiment, this paper shows that an error of 230us is reduced within 10us in case of appling the proposed method to a 4096Hz timer prescaled from 32768Hz by 8.