• 대한임베디드공학회논문지
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• 제12권4호
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• Journal of Information Display
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• 제10권1호
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• pp.37-44
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• 2009

AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, thereby having the smallest possible number of interface lines between a timing controller and column drivers. A point-to-point architecture boosts the data rate and reduces the number of interface lines, because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi-level signalling, which results in a simple clock/data recovery circuitry. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per data pair is more than 800 Mbps.

• 센서학회지
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• 제16권1호
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• pp.52-61
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• 2007

Networked embedded systems using the smart device and fieldbus technologies are now found in many industrial fields including process automation and automobiles. However the discrepancy between a node's view of current time and the rest of the system can cause many difficulties in the design and implementation of a networked system. To provide a networked system with a global reference time, the problem of clock synchronization has been intensively studied over the decades. However, many of the existing solutions, which are mainly developed for large scale distributed computer systems, cannot be directly applied to embedded systems. This paper presents a fault-tolerant clock synchronization technique that can be used for a low-cost embedded system using a CAN bus. The effectiveness of the proposed method is demonstrated with a set of microcontrollers and DC motor-based actuators.

• 대한임베디드공학회논문지
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• 제9권1호
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• pp.33-41
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• 2014

This paper presents a IEEE1588 based clock synchronization technique for a sRIO (Serial RapidIO) network which is applied to a submarine system. Clock synchronization plays a key role in the success of a networked embedded system. Recently, the IEEE1588 algorithm making use of dedicated chipset has been widely used for the synchronization of various industrial applications. However, there is no chipset available for the sRIO network that can offer many advantages, such as low latency and jitter. In this paper, the IEEE1588 algorithm for a sRIO network is implemented using only software without any dedicated chipset. The proposed approach is verified with experimental setup.

• 한국정보과학회논문지:정보통신
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• 제32권6호
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• pp.668-675
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• 2005

최근 무선 통신의 발달과 함께 임베디드 시스템의 성능 향상 및 보급률 증가로 기존의 분산 시스템 환경에 무선 임베디드 시스템들이 포함되기 시작하였다. 분산 시스템을 구성하늘 요소들 간의 동기화, 순서화, 그리고 일관성 유지를 위하여 시간 동기화는 반드시 필요하고, 지난 20여 년간 분산 시스템에서의 시간 동기화에 관한 많은 연구가 이루어져 왔다. 하지만 무선 임베디드 시스템에서의 시간 동기화는 메시지 지연과 손실이 많다는 점과 풍부하지 않은 시스템 자원을 고려해야 하므로, 기존 유선 환경에서 사용되었던 시간 동기화 알고리즘을 그대로 적용하기에는 어려운 점이 많다. 이에 본 논문에서는 IEEE 802.11 표준을 확장하여 무선 임베디드 환경에 적합한 시간 동기화 방법을 제안한다. 제안된 방법은 브로드캐스트 통신의 특성을 활용하여 무선 임베디드 환경에서의 제약 조건을 완화함으로써 높은 정확성을 제공하면서 메시지 손실을 감내하여 연속적인 시간 동기화를 제공할 수 있다. 이를 위해 마스터/슬레이브 방식의 구조에서 마스터는 시간 동기화를 위한 시간 정보를 브로드캐스트하고, 슬레이브는 편차와 편차율을 계산하여 마스터의 시간을 추정하고 동기화된 시간인 가상 시간을 계산하였다. 실험을 통해 제안된 시간 동기화 알고리즘을 사용하는 경우 200${\mu}s$ 정도의 표준 편차 범위로 동기화할 수 있음을 보였다.

• 한국군사과학기술학회지
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• 제23권5호
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• pp.516-522
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• 2020

In this paper, the frequency detector which detects the clock frequency of the embedded system is proposed and analyzed. The proposed frequency detector is consisted of filter and peak voltage detector. The clock signal is converted from square wave to triangular wave by the filter. The peak voltage of the triangular wave is determined according to the frequency response of filter. The peak voltage detector detects and holds the peak voltage of the signal. Moreover, the proposed clock frequency detector can detect the frequency within 1ms and it gives guarantee of real-time operation.

• Journal of Computing Science and Engineering
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• 제6권4호
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• pp.257-266
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• 2012

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include the clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference aware clock optimization problem, adjustable delay buffer allocation and assignment problem to support multiple voltage mode designs, and the state encoding problem for reducing peak current in sequential elements. The last topic belongs to finite state machine (FSM) design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from the clock source down to sequential elements.

• 디지털산업정보학회논문지
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• 제4권1호
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• pp.9-16
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• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• 대한임베디드공학회논문지
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• 제16권4호
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• pp.119-127
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• 2021

The aim of this paper is to propose a less conservative stabilization condition for leader-following sampled-data control of wheeled mobile robot (WMR) systems by using a clock-dependent Lyapunov function (CDLF) with looped functionals. In the leader-following WMR system, the state and input of the leader robot are measured by digital devices mounted on the following robot, and they are utilized to construct the sampled-data controller of the following robot. To design the sampled-data controller, a stabilization condition is derived by using the CDLF with looped functionals, and formulated in terms of sum of squares (SOS). The considered Lyapunov function is a polynomial form with respect to the clock related to the transmitted sampling instants. As the degree of the Lyapunov function increases, the stabilization condition becomes less conservative. This ensures that the designed controller is able to stabilize the system with a larger maximum sampling interval. The simulation results are provided to demonstrate the effectiveness of the proposed method.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.677-680
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• 2008

AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, achieving the smallest possible number of interface lines between a timing controller and source drivers. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per one data pair is more than 800Mbps.