• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.71-80
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• 2004

This paper describes embedded processor architecture design which is applicable to multimedia in mobile platform The main description is based on basic processor architecture and consideration about energy efficiency when used in mobile platform To design processor data path architecture (pipeline, branch prediction, multiple issue superscalar, function unit number) which is optimal to multimedia application and cache hierarchy and its structure, we have nut the simulation with variant architecture using MPEG4 test bench as multimedia application. We analyzed energy efficiency of architecture to check if it is applicable to mobile platform and decide basic processor architecture based on analysis result. The suggested basic processor architecture not only can be applied to mobile platform but also can be applied to basic processor architecture of configurable processor which is designed through automatic design environment.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.4
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• pp.251-259
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• 2008

This paper presents the hardware design of a 32bit floating point based processor. The processor can perform nonlinear functions such as sinusoidal functions, exponential functions, and other mathematical functions. Using the Taylor series and Newton - Raphson method, nonlinear functions are approximated. The processor is actually embedded on an FPGA chip and tested. The numerical accuracy of the functions is compared with those computed by the MATLAB and confirmed the performance of the processor.

• Journal of Digital Contents Society
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• v.18 no.5
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• pp.943-948
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• 2017

Currently, embedded systems designed for specific applications are used extensively in consumer electronics, smart phones, autonomous vehicles, robots, and plant control, etc. In addition, the importance of DRAM, which has a great influence on the performance of an embedded processor constituting an embedded system, has been increasing day by day, and research on DRAM has been actively conducted in industry and academia. Therefore, it is important to have a more accurate DRAM model in order to obtain reliable results when evaluating the performance of an embedded processor through simulation. In this paper, we developed an embedded processor simulator capable of interworking with a DRAM simulator. We also analyzed the influence of the DRAM model, which operates correctly on a cycle-by-cycle basis, on the performance of the embedded processor by using the MiBench embedded benchmark.

• ETRI Journal
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• v.27 no.5
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• pp.491-496
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• 2005

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.1
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• pp.163-169
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• 2013

Recently, the importance of embedded system is growing rapidly. In-order to satisfy the real-time constraints of the system, high performance embedded processor is required. Therefore, as in general purpose computer systems, embedded processor should be designed as multicore architecture as well. Using MiBench benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2-core to 16-core embedded processor architectures with different types of cores from simple RISC to in-order and out-of-order superscalar processors, extensively. As a result, the achievable performance is as high as 23 times over the single core embedded RISC processor.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.1
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• pp.25-29
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• 2013

Recently ARM processor's processing power has been increasing rapidly as it has been applied to consumer electronics products. Because of its computing power and low power consumption, it is used to various embedded systems.( including vision processing systems.) Embedded linux that provides well-made platform and GUI is also a powerful tool for ARM based embedded systems. So short period to develop is one of major advantages to the ARM based embedded system. However, for real-time date processing applications such as an image processing system, ARM needs additional equipments such as FPGA that is suitable to parallel processing applications. In this paper, we developed an embedded system using ARM processor and FPGA. FPGA takes time consuming image preprocessing and numerical algorithms needs floating point arithmetic and user interface are implemented using the ARM processor. Overall processing speed of the system is 60 frames/sec of VGA images.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.2
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• pp.87-93
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• 2013

In this paper, we implemented and evaluated the performance of a vector-based rasterization algorithm of 3D graphics using a SIMD-based many-core processor that consists of 4,096 processing elements. In addition, we compared the performance and efficiency of the rasterization algorithm using the many-core processor and commercial GPU (Graphics Processing Unit) system which consists of 7 GPUs and each of which have 512 cores. Experimental results showed that the SIMD-based many-core processor outperforms the commercial GPU system in terms of execution time (3.13x speedup), energy efficiency (17.5x better), and area efficiency (13.3x better). These results demonstrate that the SIMD-based many-core processor has potential as an embedded mobile processor.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.216-219
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• 2002

A novel approach of embedded systems for video coding is introduced with the main theme focused on logic-enhanced DRAM and configurable processor. This approach is aiming at reducing high computational costs and frequent memory accessing, which embedded systems are suffering with in the execution of video coding. According Co the software execution analysis, large size functions with intensive memory accesses are tuned to be executed by the logic-enhanced DRAM while small size functions repeatedly called are to be executed by dedicated instructions, which are newly introduced in the configurable processor. The proposed system can speed up H.263 video coding algorithm 7.4 times in comparison with the conventional embedded processor based system.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.255-257
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• 2006

This paper proposed a platform which includes both Network processor and DSP for flexible IED. The Network processor is one of the Intel's IXP4XX Product Line family and the DSP is one of the TI's C6000 family. An embedded Linux is ported in Network processor so that a DSP program can be downloaded to Network processor through ethernet and then downloaded to DSP. Using this method, various algorithms according to IED can be applied to the Network processor board. Maximum ten ADCs can be connected because there is a CPLD between DSP and ADC. That is, the network processor board which can measure maximum 40 channels is implemented. In DSP program, thread and double buffering methods are used not to miss voltage samples. The Network processor board is verified using a method that eight channel voltage signals converted to digital are transmitted to server through both DSP and IXP425.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.600-602
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• 2021

With the development of the mobile industry and growing interest in artificial intelligence (AI) technology, a lot of research for AI processors which applicable to embedded systems is under study. When implementing AI to embedded systems, the design should be considered the restriction of resource and power consumption. Moreover, it is efficient to include a dedicated hardware accelerator in order to complement the low computational performance of the embedded system. In this paper, we propose an stand-alone embedded AI processor. The proposed AI processor includes a hardware accelerator that is dedicated to the distance-based AI algorithm and a general-purpose MCU that supports flexible programmability for application to various embedded systems. The AI processor was designed with Verilog HDL and verified by implementing on Field Programmable Gate Array (FPGA).