• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.6
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• pp.339-345
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• 2013

This paper addresses the system lifetime maximization algorithm in multi-hop sensor network system. A multi-hop sensor network consists of many battery-driven sensor nodes that collaborate with each other to gather, process, and communicate information using wireless communications. As sensor-driven applications become increasingly integrated into our lives, we propose a energy-aware scheme where each sensor node transmits informative data with adaptive data rate to minimize system energy consumption. We show the optimal data rate to maximize the system lifetime in terms of remaining system energy. Furthermore, the proposed algorithm experimentally shows longer system lifetime in comparison with greedy algorithm.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.6
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• pp.361-367
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• 2014

This paper introduces balancing energy and memory consumption for lifetime increase of wireless sensor network. In cluster-based wireless sensor network, sensor nodes adjacent of cluster heads have a tendency to deplete their own battery energy and cluster heads occupy memory space significantly. If the nodes close to region where events occur frequently consume their energy and memory fully, network might be destroyed even though most of nodes are still alive. Therefore, it needs to balance network energy and memory with consideration of event occurrence probability so that network lifetime is increased. We show a method of balancing wireless sensor network energy and memory to organize cluster groups and elect cluster heads in terms of event occurrence probability.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.301-307
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• 2021

In addition to the revival of the Internet of Things, embedded systems, which are at the core of the Internet of Things, require intelligent control as things change. Embedded systems, however, are heavily constrained by resources such as hardware, memory, time and power. When changes are needed to firmware in an embedded system, flash Memory must be initialized and the entire firmware must be uploaded again. Therefore, it is time- and energy-efficient in that areas that do not need to be modified must also be initialized and rewritten. In this paper, we propose how to upload firmware in installments to each sector of flash memory so that only firmware can be replace the firmware in the parts that need to be modified when the firmware needs to be modified. In this paper, the proposed method was evaluated using real target board, and as a result, the time was reduced by about half.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.2
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• pp.51-58
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• 2014

As WSNs(Wireless Sensor Networks) are being deployed widely in diverse application areas, their management and maintenance become more important. Recent sensor node software takes modular software architectures in pursuit of flexible software management and energy efficient reprogramming. To realize an flexible and efficient modular architecture particularly on resource constrained mote-class sensor nodes that are implemented with MCUs(Micro-Controller Units) of a single address space. an appropriate module linking model is essential to resolve and bind the inter-module global symbols. This paper identifies a design space of module linking model and respectively their implementation frameworks. We then establish a taxonomy for module linking models by exploring the design space of module linking models. Finally, we suggest an implementation framework respectively for each module linking model in the taxonomy. We expect that this work lays the foundations for systematic innovation toward more flexible and efficient modular software architectures for WSNs.