• Journal of the Korean Data and Information Science Society
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• v.17 no.2
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• pp.437-447
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• 2006

Error Correcting Output Coding(ECOC) is used to solve multi-class problem. It is known that it improves the classification accuracy. In this paper, we compared various criteria to design code matrix while encoding. In addition. we prorpose an ensemble which uses the ability of each classifier while decoding. We investigate the justification of the proposed method through real data and synthetic data.

• Nuclear Engineering and Technology
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• v.50 no.8
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• pp.1306-1313
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• 2018

The randomness and incipient nature of certain faults in reactor systems warrant a robust and dynamic detection mechanism. Existing models and methods for fault diagnosis using different mathematical/statistical inferences lack incipient and novel faults detection capability. To this end, we propose a fault diagnosis method that utilizes the flexibility of data-driven Support Vector Machine (SVM) for component-level fault diagnosis. The technique integrates separately-built, separately-trained, specialized SVM modules capable of component-level fault diagnosis into a coherent intelligent system, with each SVM module monitoring sub-units of the reactor coolant system. To evaluate the model, marginal faults selected from the failure mode and effect analysis (FMEA) are simulated in the steam generator and pressure boundary of the Chinese CNP300 PWR (Qinshan I NPP) reactor coolant system, using a best-estimate thermal-hydraulic code, RELAP5/SCDAP Mod4.0. Multiclass SVM model is trained with component level parameters that represent the steady state and selected faults in the components. For optimization purposes, we considered and compared the performances of different multiclass models in MATLAB, using different coding matrices, as well as different kernel functions on the representative data derived from the simulation of Qinshan I NPP. An optimum predictive model - the Error Correcting Output Code (ECOC) with TenaryComplete coding matrix - was obtained from experiments, and utilized to diagnose the incipient faults. Some of the important diagnostic results and heuristic model evaluation methods are presented in this paper.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.273-276
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• 2000

Recently, Turbo code has been considered for channel coding in IMT-2000(International Mobile Telecommunication-2000) system, because it offers better error correcting capability than the traditional convolution/viterbi coding . In this paper, a turbo code decoder for speech transmission in IMT-2000 system with frame size 192 bits, constrait length K=3, generator polynomials G(5,7) and code rate R=1/3 is designed using SOVA(Soft Output Viterbi Algorithm) and block interleaver

• ETRI Journal
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• v.32 no.1
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• pp.93-101
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• 2010

A true random number generator (TRNG) is widely used to generate secure random numbers for encryption, digital signatures, authentication, and so on in crypto-systems. Since TRNG is vulnerable to environmental changes, a deterministic function is normally used to reduce bias and improve the statistical properties of the TRNG output. In this paper, we propose a linear corrector for secure TRNG. The performance of a linear corrector is bounded by the minimum distance of the corresponding linear error correcting code. However, we show that it is possible to construct a linear corrector overcoming the minimum distance limitation. The proposed linear corrector shows better performance in terms of removing bias in that it can enlarge the acceptable bias range of the raw TRNG output. Moreover, it is possible to efficiently implement this linear corrector using only XOR gates, which must have a suitable hardware size for embedded security systems.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1262-1270
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• 2017

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.430-435
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• 2018

In this paper, an improved decoding scheme for low-complexity parity-check(LCPC) code with small code length is proposed. The LCPC code is less complex than the turbo code or low density parity check(LDPC) code and requires less memory, making it suitable for communication between internet-of-things(IoT) devices. The IoT devices are required to have low complexity due to limited energy and have a low end-to-end delay time. In addition, since the packet length to be transmitted is small and the signal processing capability of the IoT terminal is small, the LCPC coding system should be as simple as possible. The LCPC code can correct all single errors and correct some of the two errors. In this paper, the proposed decoding scheme improves the bit error rate(BER) performance without increasing the complexity by correcting both errors using the soft value of the modulator output stage. As a result of the simulation using the proposed decoding scheme, the code gain of about 1.1 [dB] was obtained at the bit error rate of $10^{-5}$ compared with the existing decoding method.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.478-481
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• 2000

In this paper, we propose a joint coding system for still images using source coding and powerful error correcting code schemes. Our system comprises an LVQ (lattice vector quantization) source coding for wavelet transformed images and turbo coding for channel coding. The parameters of the image encoder and channel encoder have been optimized for an n-D (dimension) cubic lattice (D$_{n}$, Z$_{n}$), parallel concatenation fur two simple RSC (recursive systematic convolutional code) and an interleaver. For decoding the received image in the case of the AWGN (additive white gaussian noise) channel, we used an iterative joint source-channel decoding algorithm for a SISO (soft-input soft-output) MAP (maximum a posteriori) module. The performance of transmission system has been evaluated in the PSNR, BER and iteration times. A very small degradation of the PSNR and an improvement in BER were compared to a system without joint source-channel decoding at the input of the receiver.ver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.6
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• pp.540-549
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• 2013

An adaptive non-uniform quantization scheme is proposed for soft-decision error correction in NAND flash memory. Even though the conventional maximizing mutual information (MMI) quantizer shows the optimal post-FEC (forward error correction) bit error rate (BER) performance, this quantization scheme demands heavy computational overheads due to the exhaustive search to find the optimal parameter values. The proposed quantization scheme has a simple structure that is constructed by only six parameters, and the optimal values of them are found by maximizing the mutual information between the input and the output symbols. It is demonstrated that the proposed quantization scheme improves the BER performance of soft-decision decoding with only small computational overheads.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.798-804
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• 2008

This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.