• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.476-481
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• 1999

Characteristics of platinum dry etching were investigated in a cryogenic magnetized inductively coupled plasma (MICP). The problem with platinum etching is the redeposition of sputtered platinum on the sidewall. Because of the redeposits on the sidewall, the etching of patterned platinum structure produces feature sizes that exceed the original dimension of the PR size and the etch profile has needle-like shape [1]. The main object of this study was to investigate a new process technology for fence-free Pt etching As bias voltage increased, the height of fence was reduced. In cryogenic etching, the height of fence was reduced to 20% at-$190^{\circ}C$ compared with that of room temperature, however the etch profile was not still fence-free. In Ar/$SF_6$ Plasma, fence-free Pt etching was possible. As the ratio of $SF_6$ gas flow is more than 14% of total gas flow, the etch profile had no fence. Chemical reaction seemed to take place in the etch process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.2
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• pp.105-109
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• 2002

The wet etching characteristics of magnetic materials such as NiFe and CoFe were investigated in terms of etch rate and etch profile by using variouus etching solutions (etchants). Among the various etching solutions, HNO$_3$, HCl, and H$_2$SO$_4$were selected for the etching of magnetic materials and showed distinct results. In the case of NiFe films, faster etch rate were obtained with HNO$_3$solution. When NiFe films ere etched with HCl solution, white etch residues were found on the surface of etched films. From FEAES analysis of these etch residues, they were proved to be by-product from the reaction of NiFe with Cl element. CoFe thin films showed the similar trend to the case of NiFe films. They were etched fast in HNO$_3$ solution while Chl solution represented slow etching. The etch profiles of CoFe films showed smooth etch profile but revealed the partial etching around the patterns in HNO$_3$solution of relatively high concentration. It was observed that the etched surface was clean and smooth, and that white etch residues were also remained on the etched films.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.46.5-46
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• 2002

As device dimension shrinks down to sub 100nm, it is increasingly important to monitor plasma states. Plasma etching is a key means to fine patterning of thin films. Many parameters are involved in etching and each parameter has different impact on process performances, including etch rate and profile. The uniformity of etch responses should be maintained high to improve device yield and throughput. The uniformity can be measured on any etch response. The most difficulty arises when attempting to characterize etched profile. Conventionally, the profile has been estimated by measuring the slope or angle of etched pattern. One critical drawback in this measurement is that this is unable to cap...

• ETRI Journal
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• v.36 no.4
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• pp.617-624
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• 2014

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.7
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• pp.701-707
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• 2004

High aspect ratio silicon structure through deep silicon etching process have become indispensable for advanced MEMS applications. In this paper, we present the results of modified Bosch process to obtain anisotropic silicon structure with conventional Inductively Coupled Plasma (ICP) etcher instead of the expensive Bosch process systems. In modified Bosch process, etching step ($SFsub6$) / sidewall passivation ($Csub4Fsub8$) step time is much longer than commercialized Bosch scheme and process transition time is introduced between process steps to improve gas switching and RF power delivery efficiency. To optimize process parameters, etching ($SFsub6$) / sidewall passivation ($Csub4Fsub8$) time and ion energy effects on etching profile was investigated. Etch profile strongly depends on the period of etch / passivation and ion energy. Furthermore, substrate temperature during etching process was found to be an important parameter determining etching profile. Test structures with different pattern size have been etched for the comparison of the aspect ratio dependent etch rate and the formation of silicon grass. At optimized process condition, micropatterns etched with modified Bosch process showed nearly vertical sidewall and no silicon grass formation with etch rate of 1.2 ${\mu}{\textrm}{m}$/ min and the size of scallop of 250 nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.436-437
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• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.305-310
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• 2008

Deep trench etching of silicon was investigated as a function of RF source power, DC bias voltage, $C_4F_8$ gas flow rate, and $O_2$ gas addition. On increasing the RF source power from 300 W to 700 W, the etch rate was increased from $3.52{\mu}m/min$ to $7.07{\mu}m/min$. The addition of $O_2$ gas improved the etch rate and the selectivity. The highest etch rate is achieved at the $O_2$ gas addition of 12 %, The selectivity to PR was 65.75 with $O_2$ gas addition of 24 %. At DC bias voltage of -40 V and $C_4F_8$ gas flow rate of 30 seem, We were able to achieve etch rate as high as $5.25{\mu}m/min$ with good etch profile.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.213-216
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• 2001

Etching behaviors of ferroelectric YMn $O_3$ thin films were studied by an inductively coupled plasma (ICP). Etch characteristic on ferroelectric YMn $O_3$ thin film have been investigated in terms of etch rate, selectivity and etch profile. The maximum etch rate of YMn $O_3$ thin film is 300 $\AA$/min at Ar/C $l_2$ of 2/8, RF power of 800W, dc bias voltage of 200V, chamber pressure of 15mTorr and substrate temperature of 3$0^{\circ}C$. Addition of C $F_4$ gas decrease the etch rate of YMn $O_3$ thin film. From the results of XPS analysis, Y $F_{X}$ compunds were found on the surface of YMn $O_3$ thin film which is etched in Ar/C1/C $F_4$ plasma. The etch profile of YMn $O_3$ film is improved by addition of C $F_4$ gas into the Ar/C $l_2$ plasma. These results suggest that fluoride yttrium acts as a sidewall passivants which reduce the sticking coefficient of chlorine on YMn $O_3$.>.