• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.319-329
• /
• 2016

High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

• Journal of Semiconductor Engineering
• /
• v.2 no.1
• /
• pp.109-118
• /
• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.51-59
• /
• 2009

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.8
• /
• pp.65-73
• /
• 2007

This paper presents a low power CMOS continuous-time $\Sigma\Delta$ (sigma-delta) modulator for UMTS receivers. The loop filter of the continuous-time $\Sigma\Delta$ modulator consists of an active-RC filter which performs high linearity characteristics and has a simple tuning circuit for low power operating system The architecture of this modulator is the $3^{rd}-order$ 4-bit single loop configuration with a 24 of OSR (Oversampling Ratio) to increase the power efficiency. The modulator includes a half delay feedback path to compensate the excess loop delay. The experimental results of the modulator are 71dB, 65dB and 74dB of the peak SNR, peak SMR and dynamic range, respectively. The continuous-time $\Sigma\Delta$ modulator is fabricated in a 0.18-um 1P4M CMOS standard process and dissipates 15mW for a single supply voltage of 1.8V.

• Proceedings of the Korean Nuclear Society Conference
• /
• 1995.05a
• /
• pp.562-567
• /
• 1995

The concept of VLDT (Variable Low DNBR Trip), a new CPC trip function, was proposed and applied to the events of increase in secondary heat removal, such as an excess feedwater event anti an IOSGADV (Inadvertent Opening S/G Atmospheric Dump Valve). Major assumption used in this study was no time delay to LOOP (Loss of Offsite Power) after turbine trip. In case of using this VLDT function, safety criterion of DNB would not be violated under the same condition as previous analysis without any change in thermal margin.

• International Journal of Automotive Technology
• /
• v.8 no.4
• /
• pp.437-444
• /
• 2007

This paper experimentally investigates the effects of oxygen-enriched air (OEA) on the running behaviors of an LPG SI engine during both start/warm-up (SW) and hot idling (HI) stages. The experiments were performed on an air-cooled, single-cylinder, 4-stroke, LPG SI engine with an electronic fuel injection system and an electrically-heated oxygen sensor. OEA containing 23% and 25% oxygen (by volume) was supplied for the experiments. The throttle position was fixed at that of idle condition. A fueling strategy was used as following: the fuel injection pulse width (FIPW) in the first cycle of injection was set 5.05 ms, and 2.6 ms in the subsequent cycles till the achieving of closed-loop control. In closed-loop mode, the FIPW was adjusted by the ECU in terms of the oxygen sensor feedback. Instantaneous engine speed, cylinder pressure, engine-out time-resolved HC, CO and NOx emissions and excess air coefficient (EAC) were measured and compared to the intake air baseline (ambient air, 21% oxygen). The results show that during SW stage, with the increase in the oxygen concentration in the intake air, the EAC of the mixture is much closer to the stoichiometric one and more oxygen is made available for oxidation, which results in evidently-improved combustion. The ignition in the first firing cycle starts earlier and peak pressure and maximum heat release rate both notably increase. The maximum engine speed is elevated and HC and CO emissions are reduced considerably. The percent reductions in HC emissions are about 48% and 68% in CO emissions about 52% and 78%; with 23% and 25% OEA, respectively, compared to ambient air. During HI stage, with OEA, the fuel amount per cycle increases due to closed-loop control, the engine speed rises, and speed stability is improved. The HC emissions notably decrease: about 60% and 80% with 23% and 25% OEA, respectively, compared to ambient air. The CO emissions remain at the same low level as with ambient air. During both SW and HI stages, intake air oxygen enrichment causes the delay of spark timing and the increased NOx emissions.