• Journal of the Korea Computer Industry Society
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• v.2 no.6
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• pp.803-816
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• 2001

This paper presents the design of strongly fail-safe interface which transform binary signals, generated by fault-tolerant system into fail-safe signals. The strongly fail-safe property is achived by means of self-checking techniques. It can be shown for this interface to be integreated while the conventional fail-safe interface require using discrete components. This paper also presents the new implementation methods by the definitions for fail-safe system.

• Journal of Applied Reliability
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• v.1 no.1
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• pp.9-15
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• 2001

This paper modelled the fail-safe control logic through the frequency coding input and designed the 3-out of-6 self checker using the error detect coding method of information redundancy. In addition, this paper also peformed the reliability parallel numeric analysis regarding single module between fail-safe. control logic module and TMR(Triple Modular Redundancy), therefore, we achieved the result that the fail-safe control logic increases a functional reliability because of decreasing system waste cost and functional overhead rather than the existing hardware redundancy method.

• Proceedings of the KSME Conference
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• 2001.06b
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• pp.283-288
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• 2001

This study provides analytical evaluation of the Dual-Ann Work Module. The current hydraulic system was modeled using the HyPneu and analyzed to find the cause of the instability. The cause of the instability was determined to be primarily an interacting involving the pilot operated check valves and the counterbalance valves for fail safe mode of operation. A new design concept was developed to eliminate the potential for unstable operation while adequately meeting the need for a fail-safe feature.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5A
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• pp.389-396
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• 2005

In this paper, we design AVTMRWFSV(All Voting Triple Modular Redundancy With Fail-Safe Voter) System with a fail-safe output voter architecture and analyze RAMS(Reliability, Availability, Maintainability, Safety) as system failure rate. This system is compared with AVTMR system for RAMS(Reliability, Availability, Maintainability, Safety) with Markov modeling, and we can see that the system safety of AVTMRWFSV is more profitable than that of AVTMR. The dependability of AVTMRWFSV system is higher than that of AVTMR. Especially, safety is very profitable. So, this kind of system can be applied to embedded communication system and life critical systems - railway, airplane, ship, nuclear control system and so on.

• Journal of Navigation and Port Research
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• v.29 no.10 s.106
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• pp.877-882
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• 2005

It is necessary that Fail-Safe Seaway technology providing a continuous navigation solution though fault of navigation system is occurred in sea. This paper focus on signal processing of GPS receiver, one of receivers using the software radio technology to implement a integrated radio navigation system including satellite-based and ground-based navigation systems. It is difficult to implement the software GPS receivers using a commercial processor because of the heavy computational burden for processing the GPS signals in real time. This paper proposes an efficient multi-bit GPS signal processing scheme to reduce the computational burden for processing the GPS signals in the software GPS receiver. The proposed scheme uses a compression concept of the multi-bit replica signals and patterned look-up table method to generate the correlation value between the GPS signals and the replica signals.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.219-228
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• 2001

This paper presents the implementation of comparator which are Fail-Safe with respect to faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it at the Fail-Safe system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper show that these design, which was implemented with 2 level AND_ORor NOR-NOR circuit, are optimal in term of size. And it also present a formal proof that a comparator implemented as NOR-NOR PLA, based on these design, is self-testing with respect to most single faults in the presented fault model. Finally, it discuss the application of the self-testing comparator as a building block for implementing Fail-Safe Adder.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2005.10a
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• pp.37-42
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• 2005

It is necessary that Fail-Safe Seaway technology providing a continuous navigation solution though fault of navigation system is occurred in sea. This paper focus on signal processing of GPS receiver, one of receivers using the software radio technology to implement a integrated radio navigation system including satellite-based and ground-based navigation systems. It is difficult to implement the software GPS receivers using a commercial processor bemuse of the heavy computational burden for processing the GPS signals in real time. This paper proposes an efficient multi-bit GPS signal processing scheme to reduce the computational burden for processing the GPS signals in the software GPS receiver. The proposed scheme uses a compression concept of the multi-bit replica signals and patterned look-up table method to generate the correlation value between the GPS signals and the replica signals.

• Proceedings of the KSR Conference
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• 2000.05a
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• pp.336-343
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• 2000

This paper proposes the failsafe control logic. which has applied to the voting on the TMR system by using FPGA The self-detection circuit is also designed for detecting a characteristic of fault at TMR system. The fault producing in the self-detection system is largely classified among an intermittent fault, a transient fault and a permanent fault. If it is happened to the permanent fault, the system can be failed. Therefore, it is designed the logic circuit which is not transferred the permanent fault to the system after shut off output. The control logic of the Fail Safe proposed in the paper is required for a circuit integrate of device to minimize the failure happened. Therefore, it makes to design FPGA with modeling of VHDL. The circuit of the Fail Safe of TMR system is able to apply to nuclear system, rail-way system, aerospace and aircraft system which is required for high reliability.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1214-1219
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• 2002

Railway signalling system always is required high safety and reliability. The failure of the train control system can provoke a serious accident. In this paper, we show how to achieve the safety and reliability by dividing signalling system into vital and non functions, studying operational environment.

• Proceedings of the KSR Conference
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• 1999.05a
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• pp.299-306
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• 1999

The ${\mu}$-processor based-controlled system is widely used in railway signaling system. The railway signaling systems are highly required safety and reliability. It is necessary to have a fault-tolerant and fail safe concept in ${\mu}$-processor based railway signaling system. In this paper, several architectures and circuits of fault-tolerant computer system is reviewed. The basic concept of the fault-tolerant computer system will be adapted total self checking, strong fail safe, fault display circuit, logic testing circuit and system switching concepts.