• Title/Summary/Keyword: Fat-Tree

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Effects of Link Failures on Performance of Packet Scatter Schemes in Fat-Trees (Fat-Tree에서 링크 장애가 패킷분산방식의 성능에 미치는 영향)

  • Lim, Chansook
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.13 no.4
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    • pp.9-15
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    • 2013
  • Most of recent studies on data center networks are based on the assumption of symmetrical multi-rooted tree topologies such as a Fat-Tree. While packet scatter schemes are very effective for such a network topology, it is known that various failures can result in an asymmetric topology which degrades TCP performance. In this paper, we reexamine the effects of link failures on packet scatter schemes in Fat-Trees. Our simulation results show that in case of a single link failure in a large-scale Fat-Tree, packet reordering does not occur enough to degrade TCP performance. This implies that we do not necessarily need a complex scheme to make packet schemes robust to link failures.

Effects of Packet-Scatter on TCP Performance in Fat-Tree (Fat-Tree에서의 패킷분산이 TCP 성능에 미치는 영향)

  • Lim, Chansook
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.12 no.6
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    • pp.215-221
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    • 2012
  • To address the bottleneck problem in data center networks, there have been several proposals for network architectures providing high path-diversity. In devising new schemes to utilize multiple paths, one must consider the effects on TCP performance because packet reordering can make TCP perform poorly. Therefore most schemes prevent packet reordering by sending packets through one of multiple available paths. In this study we show that packet reordering does not occur severely enough to have a significant impact on TCP performance when scattering packets through all available paths between a pair of hosts in Fat-Tree. Simulation results imply that it is possible to find a low-cost solution to the TCP performance problem for Fat-Tree-like topologies.

A New Packet-level Load-balancing Scheme for Fat-Trees (Fat-Tree에서의 새로운 패킷 단위 부하분산 방식)

  • Lim, Chansook
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.13 no.2
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    • pp.53-58
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    • 2013
  • A Fat-Tree topology has multiple paths between any pair of hosts. The delay for the multiple paths with an equal number of hops depends mainly on the queuing delay. However, most of the existing load-balancing schemes do not sufficiently exploit the characteristics of Fat-Tree. In most schemes load-balancing is performed at a flow level. Packet-level load-balancing schemes usually require the availability of special transport layer protocols to address packet reordering. In this paper, we propose a new packet-level load-balancing scheme which can enhance network utilization while minimizing packet reordering in Fat-Trees. Simulation results show that the proposed scheme provides as high TCP throughput as a randomized flow-level Valiant load balancing scheme for a best case.

Performance Evaluation of a Buffered Fat-tree Network (Buffered Fat-tree Nework의 성능분석)

  • Cho, Sung-Lae;Shin, Tai-Z.;Yang, Myung-K.
    • Proceedings of the KIEE Conference
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    • 2000.11d
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    • pp.775-777
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    • 2000
  • 본 논문에서는 buffer를 장착한 양 방향성 $a{\times}b$ switch들로 구성된 fat-tree network의 성능 분석 기법을 제안하고, 분석 모형의 타당성을 검증하였다. 제안한 분석 기법은 먼저 스위치 내부의 데이터 이동 패턴을 확률식으로 표현하고. 나아가서 buffer를 장착한 $a{\times}b$ switch의 buffer 크기에 따른 정상상태 throughput을 간단한 수식으로 구할 수 있도록 하였다. 이를 토대로 buffer를 장착한 $a{\times}b$ switch로 구성된 fat-tree network의 성능을 분석하고, 제안한 분석모형의 실효성 입증을 위하여 simulation을 시행한 후 결과를 비교 분석하였다.

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Analytical modeling of a Fat-tree Network with buffered a$\times$b switches (버퍼를 장착한 a$\times$b 스위치로 구성된 Fat-tree 망의 성능분석)

  • 신태지;양명국
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.374-377
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    • 2003
  • In this paper, a performance evaluation model of the Fat-Tree network with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem in the switch network The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on the various sizes of Fat-tree networks that use the multiple a$\times$b buffered crossbar switches. It is observed that both analysis and simulation results are match closely.

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Performance Evaluation Of Fat-tree Datacenter Architecture Based On OMNeT++ (OMNeT++ 기반 Fat-tree Datacenter Architecture 성능평가)

  • Kim, Sang-Young;Lee, Byung-Jun;Jung, Dong-Young;You, Hee-Yong
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2016.01a
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    • pp.57-58
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    • 2016
  • ICT의 보급, 확대는 데이터 센터의 중요성을 높이고 보다 성능이 좋으며 체적 당 소비전력이 큰 서버를 수용할 수 있는 데이터 센터의 수요를 창출하고 있다. 현재 데이터 센터는 데이터 센터 활용 시에 구성요소들에 대한 상당한 대역폭을 필요로 하나 현 데이터센터에 적용된 토폴로지는 고성능 IP 스위치/라우터를 사용하더라도 네트워크 엣지 계층에서는 기본 활용도의 50%의 bandwidth밖에 지원하지 못한다. 따라서 이러한 문제를 해결하기 위해 OMNeT++을 이용하여 데이터 센터 토폴로지 중 하나인 Fat-tree를 모델링하고 데이터 센터 제반 환경을 구축, latency, power consumption, heat dissipation 등의 기준지표를 성능평가 하였다.

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Performance Evaluation of a Fat-tree Network with Output-Buffered $a{\times}b$ Switches (출력 버퍼형 $a{\times}b$스위치로 구성된 Fat-tree 망의 성능 분석)

  • 신태지;양명국
    • Journal of KIISE:Information Networking
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    • v.30 no.4
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    • pp.520-534
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    • 2003
  • In this paper, a performance evaluation model of the Fat-tree Network with the multiple-buffered crossbar switches is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the switch network. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. Two important parameters of the network performance, throughput and delay, are then evaluated. The proposed model takes simple and primitive switch networks, i.e., no flow control and drop packet, to demonstrate analysis procedures clearly. It, however, can not only be applied to any other complicate modern switch networks that have intelligent flow control but also estimate the performance of any size networks with multiple-buffered switches. To validate the proposed analysis model, the simulation is carried out on the various sizes of Fat-tree networks that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed.

Design of the Successive Selection Encoder by the Logical Effort for High Flash Speed ADC's (고속 플래시 AD 변환기를 위한 Successive Selection Encoder의 Logical Effort에 의한 설계)

  • Lee Kijun;Choi Kyusun;Kim Byung-soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.4 s.334
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    • pp.37-44
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    • 2005
  • In this paper, a new type of the TC-to-BC encoder for high speed flash ADC's, called the Successive Selection Encoder (SSE), is proposed. In contrast to the conventional fat tree encoder based on OR operations, the W- outputs, in the new design, are obtained directly from TC inputs through simple MUX operations. The detailed structure of the SSE has been determined systematically by the method of the logical effort and the simulation oil Hynix 0.25um process. The theoretical and experimental results show that (1) it is not required to generate one-out-of-n signals, (2) the number of gates is reduced by the factor of 1/3, and (3) the speed is improved more than 2-times, compared to the fat tree encoder. It is speculated that the SSE proposed in this study is an effective solution for bottleneck problems in high speed ADCs.

Design of a TIQ Based CMOS A/D Converter for Real Time DSP (실시간 디지털 신호처리를 위한 TIQ A/D 변환기 설계)

  • Kim, Jong-Soo
    • Journal of the Institute of Convergence Signal Processing
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    • v.8 no.3
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    • pp.205-210
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    • 2007
  • This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

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Evaluation of Ultrasound for Prediction of Carcass Meat Yield and Meat Quality in Korean Native Cattle (Hanwoo)

  • Song, Y.H.;Kim, S.J.;Lee, S.K.
    • Asian-Australasian Journal of Animal Sciences
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    • v.15 no.4
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    • pp.591-595
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    • 2002
  • Three hundred thirty five progeny testing steers of Korean beef cattle were evaluated ultrasonically for back fat thickness (BFT), longissimus muscle area (LMA) and intramuscular fat (IF) before slaughter. Class measurements associated with the Korean yield grade and quality grade were also obtained. Residual standard deviation between ultrasonic estimates and carcass measurements of BFT, LMA were 1.49 mm and $0.96cm^2$. The linear correlation coefficients (p<0.01) between ultrasonic estimates and carcass measurements of BFT, LMA and IF were 0.75, 0.57 and 0.67, respectively. Results for improving predictions of yield grade by four methods-the Korean yield grade index equation, fat depth alone, regression and decision tree methods were 75.4%, 79.6%, 64.3% and 81.4%, respectively. We conclude that the decision tree method can easily predict yield grade and is also useful for increasing prediction accuracy rate.