• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.723-726
• /
• 1998

Fault dropping is a very important part of test generation process. It is used to reduce test generation time. Test generation systems use fault simulation for the purpose of fault dropping by identifying detectable faults with generated test patterns. Two kinds of delay fault model is used in practice, path delay fault model and gate delay fault model. In this paper we propose an efficient method for gate delay test generation which shares second test vector.

• Journal of Advanced Marine Engineering and Technology
• /
• v.22 no.5
• /
• pp.687-692
• /
• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.7
• /
• pp.1394-1402
• /
• 1997

In this work, an efficient test algorithm and BIST architeture a for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect nighborhood pattern sensitive fault which could not be detected in previous march test algoarithms. The proposed test algorithm perposed test algorithm performs testing for neghborhood pattern sensitive fault using backgroung data which has been used word-oriented memory testing.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.10
• /
• pp.6666-6672
• /
• 2015

Various reflectometry methods to locate power cable fault have been studied. But, most related studies has been verifying by simulation and laboratory test and study in conditions similar with real cable fault filed was not performed due to the absence of cable fault test field. Therefore, this paper design and construct test field for the standardized performance test and the operating education of cable fault location equipments. In the constructed test, open, short, half open and poor contact fault at 100m, 200m location of cable was produced and 1km cable role was installed for maximum distance measurement test. The test field will be used in the development and standardization of cable fault location technology, and te performance evaluation and certificate test of the related equipments.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.137-140
• /
• 2000

In this paper, we have proposed an efficient test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph(STG)〔1〕 which is a kind of specification method for asynchronous circuits. To conduct a high-level test generation, we have defined a high-level fault model, called single State Transition Fault(STF) model on STG and proposed a test generation algorithm for STF model. The effectiveness of the proposed fault model and its test generation algorithm is shown by experimental results on a set of benchmarks given in the form of STG. Experimental results show that the generated test for the proposed fault model achieves high fault coverage over single input stuck-at fault model with low cost. We have also proposed extended STF model with additional gate-level information to achieve higher fault coverage in cost of longer execution time.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.12
• /
• pp.1964-1969
• /
• 2012

This paper presents to verify the selective grounding fault protective relaying technique for the ungrounded DC traction power supply system. This system selectively blocks fault section when grounding fault occurred. In order to perform this verification, field test facilities have been installed on Oesam substation and Worldcup-Stadium substation, and field test process has been suggested. Also, selective grounding fault protective relaying components and rail voltage reduction device have been tested with the various trial examinations. In order to compare and evaluate performance of the selective grounding fault protective relaying function, field test system was modeled and the system fault simulation results were compared and evaluated with the field test result. Performance of selective grounding fault protective relaying function was evaluated with the above-mentioned process, and the fact that the system recognizes fault section irrespective of insulation between rail and ground and fault resistance from grounding fault.

• Journal of Electrical Engineering and Technology
• /
• v.7 no.5
• /
• pp.797-806
• /
• 2012

Fault detection and isolation (FDI) algorithms provide fault monitoring methods in GPS measurement to isolate abnormal signals from the GPS satellites or the acquired signal in receiver. In order to monitor the occurred faults, FDI generates test statistics and decides the case that is beyond a designed threshold as a fault. For such problem of fault detection and isolation, this paper presents and evaluates position domain integrity monitoring methods by formulating various pseudorange prediction methods and investigating the resulting test statistics. In particular, precise measurements like carrier phase and Doppler rate are employed under the assumption of fault free carrier signal. The presented position domain algorithm contains the following process; first a common pseudorange prediction formula is defined with the proposed variations in pseudorange differential update. Next, a threshold computation is proposed with the test statistics distribution considering the elevation angle. Then, by examining the test statistics, fault detection and isolation is done for each satellite channel. To verify the performance, simulations using the presented fault detection methods are done for an ideal and real fault case, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.32-40
• /
• 2009

In order to reduce time-to-market, the demand for fast fault diagnosis has been increased. In this paper, a fault dropping technique with fault candidate ordering and test pattern ordering for fast fault diagnosis is proposed. Experimental results using the full-scanned ISCAS 89 benchmark circuits show the efficiency of the fault dropping technique with fault candidate ordering and test pattern ordering.

• Electrical & Electronic Materials
• /
• v.10 no.4
• /
• pp.349-354
• /
• 1997

This paper aims at studying the improvement of test method for t-weight sensitive fault (t-wsf) detect. The development of RAM fabrication technology results in not only the increase at device density on chips but also the decrease in line widths in VLSI. But, the chip size that was large and complex is shortened and simplified while the cost of chips remains at the present level, in many cases, even lowering. First of all, The testing patterns for RAM fault detect, which is apt to be complicated , need to be simplified. This new testing method made use of Local Lower Bound (L.L.B) which has the memory with the beginning pattern of 0(l) and the finishing pattern of 0(1). The proposed testing patterns can detect all of RAM faults which contain stuck-at faults, coupling faults. The number of operation is 6N at 1-weight sensitive fault, 9,5N at 2-weight sensitive fault, 7N at 3-weight sensitive fault, and 3N at 4-weight sensitive fault. This test techniques can reduce the number of test pattern in memory cells, saving much more time in test, This testing patterns can detect all static weight sensitive faults and pattern sensitive faults in RAM.

• Journal of Computing Science and Engineering
• /
• v.9 no.3
• /
• pp.142-154
• /
• 2015

Fault localization techniques help locate faults in source codes by exploiting collected test information and have shown promising results. To precisely locate faults, the techniques require a large number of test cases that sufficiently exercise the executable statements together with the label information of each test case as a failure or a success. However, during the process of software development, developers may not have high-coverage test cases to effectively locate faults. With the test case generation techniques, a large number of test cases without expected outputs can be automatically generated. Whereas the execution results for generated test cases need to be inspected by developers, which brings much manual effort and potentially hampers fault-localization effectiveness. To address this problem, this paper presents a method to select a few test cases from a number of test cases without expected outputs for result inspection, and in the meantime selected test cases can still support effective fault localization. The experimental results show that our approach can significantly reduce the number of test cases that need to be inspected by developers and the effectiveness of fault localization techniques is close to that of whole test cases.