• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.4
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• pp.3-10
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• 1999

More concerns are concentrated in finite fields arithmetic as finite fields being applied for Elliptic curve cryptosystem coding theory and etc. Finite fields arithmetic is affected in represen -tation of those. Optimal normal basis is effective in hardware implementation and polynomial field which is effective in the basis conversion with optimal normal basis and show that the arithmetic of finite field with the basis is effective in software implementation.

• Journal of information and communication convergence engineering
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• v.9 no.4
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.227-233
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• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1207-1212
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• 2013

Arithmetic operations over finite fields are widely used in coding theory and cryptography. In both of these applications, there is a need to design low complexity finite field arithmetic units. The complexity of such a unit largely depends on how the field elements are represented. Among them, representation of elements using a optimal normal basis is quite attractive. Using an algorithm minimizing the number of 1's of multiplication matrix, in this paper, we propose a multiplier which is time and area efficient over finite fields with optimal normal basis.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.70-75
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• 2016

This paper proposes the constructing method of effective multiplier based on the finite fields in case of P=2. The proposed multiplier is constructed by polynomial arithmetic part, mod F(${\alpha}$) part and modular arithmetic part. Also, each arithmetic parts can extend according to m because of it have modular structure, and it is adopted VLSI because of use AND gate and XOR gate only. The proposed multiplier is more compact, regularity, normalization and extensibility compare with earlier multiplier. Also, it is able to apply several fields in recent hot issue IoT configuration.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.317-322
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• 2010

This paper presents an algorithm generating inverse element over finite fields GF($3^m$), and constructing method of inverse element generator based on inverse element generating algorithm. An inverse computing method of an element over GF($3^m$) which corresponds to a polynomial over GF($3^m$) with order less than equal to m-1. Here, the computation is based on multiplication, square and cube method derived from the mathematics properties over finite fields.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.29-33
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• 1978

In this paper, the properties of Galois fields defined over any finite field are analysed to derive Galois switching functions and the arithmetic operation methods over any finite field are showed. The polynomial expansions over finite fields by Lagrange's interpolation method are derived and proved. The results are applied to multivalued single variable logic networks.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.528-535
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• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.