• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.2
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• pp.428-431
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• 2007

A floating-point number system is used to represent a wide range of real numbers using finite number of bits. The standard the IEEE adopted in 1987 divides the range of real numbers into intervals of [$2^E,2^{E+1}$), where E is an Integer represented with finite bits, and defines equally spaced equal counts of discrete numbers in each interval. Since the numbers are defined discretely, not only the number representation itself includes errors but in floating-point arithmetic some strange behaviors are observed which cannot be agreed with the real world arithmetic. In this paper errors with floating-point number representation, those with arithmetic operations, and those due to order of arithmetic operations are analyzed theoretically with help of and verification with the results of some MATLAB program executions.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.3
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• pp.96-105
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• 1992

The use of fixed-point digital signal processors, such as the TMS 320C25, requires scaling of data at each arithmetic step to prevent overflows while keeping the accuracy. A software which automatizes this process is developed for TMS 320C25. The programmers use a model of a hypothetical floating-point digital signal processor and a floating-point format for data representation. However, the program and data are automatically translated to a fixed-point version by this software. Thus, the execution speed is not sacrificed. A fixed-point variable has a unique binary-point location, which is dependent on the range of the variable. The range is estimated from the floating-point simulation. The number of shifts needed for arithmetic or data transfer step is determined by the binary-points of the variables associated with the operation. A fixed-point code generator is also developed by using the proposed automatic scaling software. This code generator produces floating-point assembly programs from the specifiations of FIR, IIR, and adaptive transversal filters, then floating-point programs are transformed to fixed-point versions by the automatic scaling software.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1593-1600
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• 2009

There are two major algorithms to find a square root of floating point number, one is the Newton_Raphson algorithm and GoldSchmidt algorithm which calculate it approximately by iterating multiplications and the other is SRT algorithm which calculates it exactly by iterating subtractions. This paper proposes an exact floating point square root algorithm using only multiplication. At first an approximate inverse square root is calculated by Newton_Raphson algorithm, and then an exact square root algorithm by reducing an error in it and a compensation algorithm of it are proposed. The proposed algorithm is verified to calculate all of numbers in a single precision floating point number and 1 billion random numbers in a double precision floating point number. The proposed algorithm requires only the multipliers without another hardware, so it can be widely used in an embedded system and mobile production which requires an efact square root of floating point number.

• 한국신재생에너지학회:학술대회논문집
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• 2005.11a
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• pp.665-665
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• 2005

The existing DSP for utility interactive photovoltaic generation system control generally uses floating point process type. Because it is easy to use for number crunching, however, it is too late and too expensive. Fixed point process DSP TMS320F2812, has high control speed and is rather inexpensive. A very complicated real system can be simulated using hardware-in-the-loop (HIL) system in a virtual environment Therefore, HIL system can speed up research and development process with a little effort. Also current DSP for utility interactive photovoltaic generation system adopts floating point process type, which is easy to use for number crunching. However, fixed point process DSF, TMS320F2812, has high control speed and is rather inexpensive. This paper presents more efficient method for MPPT control using TMS320F2812 along with HIL System.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Proceedings of the Korea Water Resources Association Conference
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• 2017.05a
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• pp.514-514
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• 2017

Floating breakwaters were treated as solid bodies without any perforation in previous studies. In this study, however, a floating breakwater is perforated to allow the partial absorption of the energy produced by incident waves and an air chamber is placed in the upper part to control the breakwater draft. A series of laboratory experiments for a floating breakwater installed with a mooring system are carried out. In general, a mooring system can be classified by the number of mooring points, the shape of the mooring lines, and the degree of line tension. In this study, a four-point mooring is employed since it is relatively easier to analyze the measured results. Furthermore, both the tension-leg and the catenary mooring systems have been adopted to compare the performance of the system. In laboratory experiments, the hydraulic characteristics of a floating breakwater were obtained and analyzed in detail. Also, a hydraulic model test was carried out on variable changes by changing the mooring angle and thickness of perforated wall. A hydraulic model was designed to produce wave energy by generating a vortex with the existing reflection method. Analysis on wave changes was conducted and the flow field around the floating breakwater and draft area, which have elastic behavior, was collected using the PIV system. From the test results the strong vortex was identified in the draft area of the perforated both-sides-type floating breakwater. Also, the wave control performance of the floating breakwater was improved due to the vortex produced as the tension in the mooring line decreased.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1332-1344
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• 1996

This paper presents a pipelined floating point multiplier(FMUL) for superscalar microprocessors that conbines radix-16 recoding scheme based on signed-digit(SD) number system and new rouding and normalization scheme. The new rounding and normalization scheme enable the FMUL to compute sticky bit in parallel with multiple operation and elminate timing delay due to post-normalization. By expoliting SD radix-16 recoding scheme, we can achieves further reduction of silicon area and computation time. The FMUL can execute signle-precision or double-precision floating-point multiply operation through three-stage pipelined datapath and support IEEE standard 754. The algorithm andstructure of the designed multiplier have been successfully verified through Verilog HOL modeling and simulation.

• Journal of Microbiology
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• v.45 no.2
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• pp.122-127
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• 2007

Factors indicating culture status of two Spirulina platensis strains were monitored in a batch mode cultivation for 36 days. Changing mode in all factors showed a common turning point, indicating shift of cell or culture status. Mean biomass productivity was highly sustained until day 22, chlorophyll a concentration peaked on day 22, pH value was > 12 on day 22, coil number was abruptly shortened on day 22, and floating activity was sustained at greater than 79% after day 22, indicating that day 22 is a criterion reflecting phase-transfer in cell physiology in a batch culture system. Many of these changes may have been caused by increased pH, suggesting that pH control is essential for mass production of S. platensis. Fluctuations in floating activity were likely induced by the number of cellular gas vacuoles. Consequently, coil number per trichome and floating activity of S. platensis could readily act as simple indicators for determination of culture status or harvesting time of cells.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.