• Journal of the Korean Mathematical Society
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• v.51 no.1
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• pp.55-65
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• 2014

A graph G is called a fractional (g, f, n)-critical graph if any n vertices are removed from G, then the resulting graph admits a fractional (g, f)-factor. In this paper, we determine the new toughness condition for fractional (g, f, n)-critical graphs. It is proved that G is fractional (g, f, n)-critical if $t(G){\geq}\frac{b^2-1+bn}{a}$. This bound is sharp in some sense. Furthermore, the best toughness condition for fractional (a, b, n)-critical graphs is given.

• Journal of applied mathematics & informatics
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• v.25 no.1_2
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• pp.283-291
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• 2007

A simple graph G is said to be fractional n-factor-critical if after deleting any n vertices the remaining subgraph still has a fractional perfect matching. For fractional n-factor-criticality, in this paper, one necessary and sufficient condition, and three sufficient conditions related to maximum matching, complete closure are given.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2444-2450
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• 2011

In this paper, we propose the low fractional spur phase-locked loop(PLL) with multiple phase-frequency detector(PFD). The fractional spurs are suppressed by using a new PFD. The new PFD architecture with two different edge detection methods is used to suppress the fractional spur by limiting a maximum width of the output signals of PFD. The proposed PLL was simulated by HSPICE using a 0.35m CMOS parameters. The simulation results show that the proposed PLL is able to suppress fractional spurs with fast locking.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2716-2724
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• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1558-1563
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• 2007

In this paper, phase-locked loop (PLL) of a combinational architecture consisting of an adaptive bandwidth and fractional-N is presented to improve performances and reduce the order of ${\Delta}{\Sigma}$ modulator while maintaining equivalent or better performance with fast locking. The architecture of adaptive bandwidth PLL was simulated by HSPICE using 0.35m CMOS parameters. The behavioral simulation of the proposed adaptive bandwidth fractional-N PLL with a ${\Delta}{\Sigma}$ modulator was carried out by using MatLab to determine if the architecture could achieve the objectives. The HSPICE simulation showed that this type of PLL was able to fast locking, and reduce fractional spurs about 20dB.

• Journal of applied mathematics & informatics
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• v.34 no.5_6
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• pp.435-441
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• 2016

Let G be a graph, and let g, f be two nonnegative integer-valued functions defined on V (G) with g(x) ≤ f(x) for each x ∈ V (G). A graph G is called a fractional (g, f, n)-critical graph if after deleting any n vertices of G the remaining graph of G admits a fractional (g, f)-factor. In this paper, we obtain a binding number condition for a graph to be a fractional (g, f, n)-critical graph, which is an extension of Zhou and Shen's previous result (S. Zhou, Q. Shen, On fractional (f, n)-critical graphs, Inform. Process. Lett. 109(2009)811-815). Furthermore, it is shown that the lower bound on the binding number condition is sharp.

• Journal of the Chungcheong Mathematical Society
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• v.25 no.3
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• pp.527-529
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• 2012

It is proved that the fractional Sobolev spaces $W^s_p(\mathbb{R}^n)$ 0 < $s$ < $n$, are compactly embedded into Lebesgue spaces $L^q(\Omega)$ for some bounded set $\Omega$­.

• Journal of the Chungcheong Mathematical Society
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• v.25 no.2
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• pp.149-157
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• 2012

By means of fractional calculus techniques, we find explicit solutions of confluent hypergeometric equations. We use the N-fractional calculus operator $N^{\mu}$ method to derive the solutions of these equations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.170-183
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• 2013

This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ${\Delta}{\Sigma}$ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ${\Delta}{\Sigma}$ fractional-N PLLs are discussed with simulation and hardware results. High-order ${\Delta}{\Sigma}$ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.

• Korean Journal of Mathematics
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• v.27 no.2
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• pp.357-374
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• 2019

In this paper, first we obtain some inequalities of Hadamard type for (h - m)-convex functions via Caputo k-fractional derivatives. Secondly, two integral identities including the (n + 1) and (n+ 2) order derivatives of a given function via Caputo k-fractional derivatives have been established. Using these identities estimations of Hadamard type integral inequalities for the Caputo k-fractional derivatives have been proved.